NDLI: Hardware overhead analysis of programmability in ARX crypto processing

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Hardware overhead analysis of programmability in ARX crypto processing

Content Provider	ACM Digital Library
Author	El-Hadedy, Mohamed Skadron, Kevin
Abstract	This paper evaluates the area and performance overhead of a programmable cryptographic accelerator specialized to support ARX (Add, Rotate, and Xor) based encryption standards, which are common in symmetric cryptography. This overhead is measured by comparing to a variety of custom ARX implementations optimized specifically for π -- Cipher. This is a new algorithm for authenticated encryption that offers advantages over AES-GCM and is a candidate in the CAESAR competition. The programmable processor is designed to accommodate different word sizes, different block sizes and different security levels. The custom variants require separate versions to support these diverse capabilities. We find that the overhead of the programmability is quite high. For example, we implemented the Programmable Processing Element PPE in 227 slices, achieving a throughput of about 1.2 Gbps/block, regardless of the word size. In comparison, our best custom 64-bit implementation so far requires 445 slices, achieving 3.09 Gbps. This means that two PPEs running in parallel can achieve 75% of the throughput of the custom 64-bit solution, while providing flexibility to support diverse cryptographic standards.
Starting Page	1
Ending Page	4
Page Count	4
File Format	PDF
ISBN	9781450334839
DOI	10.1145/2768566.2768574
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-06-14
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpga Caesar Encryption Crypto-systems
Content Type	Text
Resource Type	Article

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