NDLI: Use of the subscripted DALG in submodule testing with applications in cellular arrays

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“IBM perspectives on the electrical design automation industry” (keynote address)

Fundamentals of parallel logic simulation

Statistics on logic simulation

Exploiting parallelism in a switch-level simulation machine

A version server for computer-aided design data

Semantics of CAD objects for generalized databases

DOSS: a storage system for design data

A design utility manager: the ADAM planning engine

VLSI CAD tool integration using the Ulysses environment

An expert-system paradigm for design

Tutorial on parallel processing for design automation applications (tutorial session)

Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference

SOCRATES: a system for automatically synthesizing and optimizing combinational logic

MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators

Technology adaption in logic synthesis

A new algorithm for floorplan design

A linear algorithm to find a rectangular dual of a planar triangulated graph

Two-dimensional compaction by “zone refining”

Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout

GEMS: an automatic layout tool for MIMOLA schematics

An object-oriented visual simulator for microprogram development

A monitor for complex CAD systems

Automating the generation of interactive interfaces

SIMMOS: a multiple-delay switch-level simulator

SLS—a fast switch level simulator for verification and fault coverage analysis

MOS circuit models in Network C

CINNAMON: coupled integration and nodal analysis of MOS networks

A workstation-mixed model circuit simulator

Generating essential primes for a Boolean function with multiple-valued inputs

A new method for verifying sequential circuits

A logic verifier based on Boolean comparison

Reasoning about digital systems using temporal logic

SCAT—a new statistical timing verifier in a silicon compiler system

An accuration delay modeling technique for switch-level timing verification

Yield of VLSI circuits (panel session): myths vs. reality

Robust test generation algorithm for stuck-open fault in CMOS circuits

Transistor-level test generation for physical failures in CMOS circuits

An effective test generation system for sequential circuits

A heuristic chip-level test generation algorithm

HAL: a multi-paradigm approach to automatic data path synthesis

A new synthesis for the MIMOLA software system

Synthesis of VLSI systems with the CAMAD design aid

Synthesis of concurrent modular controllers from algorithmic descriptions

Simulated annealing and combinatorial optimization

Integrated placement/routing in sliced layouts

On the relative placement and the transportation problem for standard-cell layout

Analysis of placement procedures for VLSI standard cell layout

An overview of VHDL language and technology

A tutorial introduction to the electronic design interchange format (tutorial session)

A unified treatment of PLA faults by Boolean differences

Design-for-testability of PLA's using statistical cooling

Use of the subscripted DALG in submodule testing with applications in cellular arrays

Principles of design automatioon system for very large scale computer design

An extensive logic simulation method of very large scale computer design

Establishment of higher level logic design for very large scale computer

Computer aided (CA) tools integration and related standards development (panel session)

Self-testing with correlated faults

Automatic generation of self-test programs—a new feature of the MIMOLA design system

Efficient spare allocation in reconfigurable arrays

Incremental logic synthesis through gate logic structure identification

An effective delay analysis system for a large scale computer design

Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs

A time and space efficient net extractor

Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning

A technology independent approach to hierarchical IC layout extraction

TimberWolf3.2: a new standard cell placement and global routing package

Vanguard: a chip physical design system

Automated layout synthesis in the YASC silicon compiler

Sehwa: a program for synthesis of pipelines

MAHA: a program for datapath synthesis

PLEST: a program for area estimation of VLSI integrated circuits

Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions

Hierarchial global wiring for custom chip design

An industrial world channel router for non-rectangular channels

Chameleon: a new multi-layer channel router

Flow graph representation

A design rule database system to support technology-adaptable applications

STL—a high level language for simulation and test

GENERIC: a silicon compiler support language

Knowlege-based expert systems and their application(tutorial session

On fault modeling for dynamic MOS circuits

Effectiveness of heuristics measures for automatic test pattern generation

Mixed-level fault coverage estimation

Optimal order of the VLSI IC testing sequence

Multiprocessor-based placement by simulated annealing

A new routing algorithm and its hardware implementation

HAL II: a mixed level hardware logic simulation system

An empirical analysis of the performance of a multiprocessor-based circuit simulator

A rule-based logic circuit synthesis system for CMOS gate arrays

Flute—a floorplanning agent for full custom VLSI design

Knowledge-based optimal IIL generator from conventional logic circuit descriptions

PEARL: an expert system for power supply layout

Automatic placement a review of current techniques (tutorial session)

Floor planning systems (panel session)

GENIE: a generalized array optimizer for VLSI synthesis

Comparison of CMOS PLA and polycell representations of control logic

An implementation of a state assignment heuristic

Escher—a geometrical layout system for recursively defined circuits

MADMACS: a new VLSI layout macro editor

A language for describing rectilinear Steiner tree configurations

Dual quadtree representation for VLSI designs

Precedent-based manipulation of VLSI structures

A frame based system for representing knowledge about VLSI design: a proposal

A rule-based approach to unifying functional and fault simulation and timing verification

Plug-in timing models for an abstract timing verifier

Delay reduction using simulated annealing

A new approach to multi-layer PCB routing with short vias

A preprocessor for the via minimization problem

Near-optimal n-layer channel routing

Principles of the SYCO compiler

DATAPATH: a CMOS data path silicon assembler

An intelligent module generator environment

HAPPI: a chip compiler based on double-level-metal technology

An object-oriented, procedural database for VLSI chip planning

An automated database design tool using the ELKA conceptual model

A database interface for an integrated CAD system

Rules-based object clustering: a data structure for symbolic VLSI synthesis and analysis

Simulating and controlling the effects of transmission line impedance mismatches

A delay test system for high speed logic LSI's

Router system for printed wiring boards of very high-speed, very large-scale computers

Global forced hierarchical router

Hierarchical dynamic router

A parameter-driven router

Early verification of prototype tooling for IC designs

Algorithms for global routing

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