NDLI: Architectural partitioning of control memory for application specific programmable processors

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Conference Committee

Technical Program Committee

Tutorial 1: Practical Aspects of Formal Hardware Verification

Tutorial 2: Hardware/Software Codesign of Embedded Systems

Tutorial 3: Optimization Techniques for Low Power VLSI Circuits

Tutorial 4: The Systematic Design of Asynchronous Circuits

Panel: Chief Technologists Tell All What' s Hot? What' s Not? What' s Next?

Panel: Are Parameterized Cores a Serious Business?

Efficient validity checking for processor verification

The formal verification of a pipelined double-precision IEEE floating-point multiplier

Extracting RTL models from transistor netlists

Switching activity analysis using Boolean approximation method

Estimation and bounding of energy consumption in burst-mode control circuits

Statistical estimation of sequential circuit activity

Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect

Generating sparse partial inductance matrices with guaranteed stability

Addressing high frequency effects in VLSI interconnects with full wave model and CFH

Clock distribution design and verification for PowerPC microprocessors

Activity-driven clock design for low power circuits

Bounded-skew clock and Steiner routing under Elmore delay

Who are the variables in your neighborhood

Efficient construction of binary moment diagrams for verifying arithmetic circuits

Be careful with don't cares

Pattern generation for a deterministic BIST scheme

Test register insertion with minimum hardware cost

Pseudo-random testing and signature analysis for mixed-signal circuits

Efficient and accurate transient simulation in charge-voltage plane

A fast wavelet collocation method for high-speed VLSI circuit simulation

A formal approach to nonlinear analog circuit verification

Constrained multivariable optimization of transmission lines with general topologies

Optimal wire sizing and buffer insertion for low power and a generalized delay model

A sequential quadratic programming approach to concurrent gate and wire sizing

High-density reachability analysis

Hybrid decision diagrams

Synthesizing Petri nets from state-based models

Design verification via simulation and automatic test pattern generation

On adaptive diagnostic test generation

Diagnosis of realistic bridging faults with single stuck-at information

SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits

Extraction of circuit models for substrate cross-talk

Stable and efficient reduction of substrate model networks using congruence transforms

New algorithms for min-cut replication in partitioned circuits

Linear decomposition algorithm for VLSI design applications

A gradient method on the initial partition of Fiduccia-Mattheyses algorithm

Binary decision diagrams and beyond: enabling technologies for formal verification

Coping with RC(L) interconnect design headaches

Efficient orthonormality testing for synthesis with pass-transistor selectors

Logic decomposition during technology mapping

Efficient use of large don't cares in high-level and logic synthesis

Interface co-synthesis techniques for embedded systems

Communication synthesis for distributed embedded systems

Design-for-debugging of application specific designs

A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization

Acceleration techniques for dynamic vector compaction

LOT: logic optimization with testability—new transformations using recursive learning

An empirical model for accurate estimation of routing delay in FPGAs

Performance-driven simultaneous place and route for island-style FPGAs

Board-level multi-terminal net routing for FPGA-based logic emulation

Technology mapping for field-programmable gate arrays using integer programming

Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture

Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits

Hierarchical timing analysis using conditional delays

Timing Analysis with Known False Sub Graphs

Performance estimation of embedded software with instruction cache modeling

Memory bank and register allocation in software synthesis for ASIPs

Instruction selection using binate covering for code size optimization

Fast discrete function evaluation using decision diagrams

Fast functional simulation using branching programs

Gate-level simulation of digital circuits using multi-valued Boolean algebras

An iterative gate sizing approach with accurate delay evaluation

Boolean techniques for low power driven re-synthesis

Two-level logic minimization for low power

PARAS: system-level concurrent partitioning and scheduling

Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques

System partitioning to maximize sleep time

A delay model for logic synthesis of continuously-sized networks

Power vs. delay in gate sizing: conflicting objectives?

Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization

Rectangle-packing-based module placement

An optimal algorithm for area minimization of slicing floorplans

Re-engineering of timing constrained placements for regular architectures

Power estimation techniques for integrated circuits

CAD challenges in multimedia computing

Address generation for memories containing multiple arrays

Background memory management for dynamic data structure intensive processing systems

Architectural partitioning of control memory for application specific programmable processors

Cost-free scan: a low-overhead scan path design methodology

A controller-based design-for-testability technique for controller-data path circuits

On testable multipliers for fixed-width data path architectures

A high-level design and optimization tool for analog RF receiver front-ends

A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters

Statistical behavioral modeling and characterization of A/D converters

Optimal wiresizing for interconnects with multiple sources

Post routing performance optimization via multi-link insertion and non-uniform wiresizing

Single-layer fanout routing and routability analysis for Ball Grid Arrays

Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications

Time-Constrained Loop Pipelining

An iterative improvement algorithm for low power data path synthesis

Symbolic hazard-free minimization and encoding of asynchronous finite state machines

Sequential synthesis using S1S

Multi-level logic optimization of FSM networks

Design based analog testing by Characteristic Observation Inference

Dynamic test signal design for analog ICs

Impulse response fault model and fault extraction for functional level analog circuit diagnosis

Delay optimal partitioning targeting low power VLSI circuits

PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists

Circuit partitioning with logic perturbation

Phantom redundancy: a high-level synthesis approach for manufacturability

APPlaUSE: A&barbelow;rea and p&barbelow;erformance optimization in a u&barbelow;nified placement and s&barbelow;ynthesis e&barbelow;nvironment

Synthesis of multiplier-less FIR filters with minimum number of additions

A multiple-dominance switch-level model for simulation of short faults

Fault emulation: a new approach to fault grading

Functional test generation for delay faults in combinational circuits

A novel methodology for statistical parameter extraction

Relaxation-based harmonic balance technique for semiconductor device simulation

Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels

A unified approach to topology generation and area optimization of general floorplans

A timing-driven data path layout synthesis with integer programming

Signal integrity optimization on the pad assignment for high-speed VLSI design

Multi-level logic optimization of FSM networks

Timing analysis with known false sub graphs

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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