NDLI: System partitioning to maximize sleep time

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Multi-level logic optimization of FSM networks

Timing analysis with known false sub graphs

System partitioning to maximize sleep time

Content Provider	ACM Digital Library
Author	Farrahi, Amir H. Sarrafzadeh, Majid
Abstract	Abstract: Partitioning of a system to maximize exploitable sleep time for low-power synthesis is discussed. The motivation is to deactivate the memory refresh circuitry, apply power down or disable the clock signals during the inactive periods of operation of circuit elements, and thus minimize the power consumption. Since it is impractical to have a separate set of control signals for each circuit element (otherwise, the control itself would consume a lot of power), it is advisable to partition a circuit based on the activity patterns of its elements so that the partitions can be switched into sleep mode for long periods of time. In this paper, we formulate this partitioning problem and show that it is NP-hard. We present Geo-Part, a geometric partitioning heuristic for this problem. An efficient implementation of Geo-Part using segment tree data structure is discussed. Experimental results are encouraging.
Starting Page	452
Ending Page	455
Page Count	4
File Format	PDF
ISBN	0818672137
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1995-12-01
Access Restriction	Subscribed
Subject Keyword	Exploitable sleep time Logic cad Vlsi Segment tree data structure Geometric partitioning heuristic Integrated circuit design Memory refresh circuitry Geo-part Circuit cad Low-power synthesis System partitioning Partitioning problem Logic partitioning Circuit optimisation
Content Type	Text
Resource Type	Article

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