NDLI: Parallel sections: scaling system-level data-structures

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Parallel sections: scaling system-level data-structures

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Parallel sections: scaling system-level data-structures

Content Provider	ACM Digital Library
Author	Stamler, Timothy Parmer, Gabriel Wang, Qi
Abstract	As systems continue to increase the number of cores within cache coherency domains, traditional techniques for enabling parallel computation on data-structures are increasingly strained. A single contended cache-line bouncing between different caches can prohibit continued performance gains with additional cores. New abstractions and mechanisms are required to reassess how data-structure consistency can be provided, while maintaining stable per-core access latencies. This paper presents the Parallel Sections (ParSec) abstraction for mediating access to shared data-structures. Fundamental to the approach is a new form of scalable memory reclamation that leverages fast local access to real-time to globally order system events. This approach attempts to minimize coherency-traffic, while harnessing the benefit of shared read-mostly cache-lines. We show that the co-management of scalable memory reclamation, memory allocation, locking, and namespace management enables scalable system service implementation. We apply ParSec to both memcached, and virtual memory management in a microkernel, and find order-of magnitude performance increases on a four socket, 40 core machine, and 30x lower 99th percentile latencies for virtual memory management.
Starting Page	1
Ending Page	15
Page Count	15
File Format	PDF
ISBN	9781450342407
DOI	10.1145/2901318.2901356
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-04-18
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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