NDLI: A hardware spinal decoder

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A hardware spinal decoder

Content Provider	ACM Digital Library
Author	Perry, Jonathan Balakrishnan, Hari Iannucci, Peter A. Fleming, Kermin Elliott Shah, Devavrat
Abstract	Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as greatly reduced latency and complexity. The enabling architectural feature is a novel alpha-beta incremental approximate selection algorithm. We also present a method for obtaining hints which anticipate successful or failed decoding, permitting early termination and/or feedback-driven adaptation of the decoding parameters. We have validated our implementation in FPGA with on-air testing. Provisional hardware synthesis suggests that a near-capacity implementation of spinal codes can achieve a throughput of 12.5 Mbps in a 65 nm technology while using substantially less area than competitive 3GPP turbo code implementations.
Starting Page	151
Ending Page	162
Page Count	12
File Format	PDF
ISBN	9781450316859
DOI	10.1145/2396556.2396593
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-10-29
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Spinal Wireless Architecture Rateless Decoder
Content Type	Text
Resource Type	Article

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