NDLI: Integrated scratchpad memory optimization and task scheduling for MPSoC architectures

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Integrated scratchpad memory optimization and task scheduling for MPSoC architectures

Content Provider	ACM Digital Library
Author	Suhendra, Vivy Mitra, Tulika Raghavan, Chandrashekar
Abstract	Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a complex electronic system. An MPSoC architecture is, in general, customized for an embedded application. A critical component of this customization process is the on-chip memory system configuration. Embedded systems increasingly employ software-controlled scratchpad memory(SPM) due to its inherent advantages in terms of area, energy, and timing predictability compared to caches. An application-specific flexible partitioning of the on-chip SPM budget among the processors is critical for performance optimization. Moreover, scheduling the tasks of an application on to the processors and partitioning the SPM are inter-dependent even though these steps are decoupled in the traditional design space exploration process. In this work, we design an integrated task mapping, scheduling, SPM partitioning, and data allocation technique based on Integer Linear Programming(ILP)formulation. Our ILP formulation explores the optimal performance limit and shows that integrated task schedul-ing and SPM optimization improves performance by up to 80% for embedded applications.
Starting Page	401
Ending Page	410
Page Count	10
File Format	PDF
ISBN	1595935436
DOI	10.1145/1176760.1176809
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-10-22
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Mpsoc Task mapping Scheduling Scratchpad memory
Content Type	Text
Resource Type	Article

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