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Content Provider | ACM Digital Library |
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Author | Auerbach, Isaac L. |
Abstract | A parallel static magnetic memory system was designed to increaseby 100 words the fast access-time memory capacity of the ENIAC. Atpresent the ENIAC has only 20 words of internal memory, in the formof electronic accumulators. This small memory capacity limits thesize of the problem that can be programmed without repeatedreference to the external punched-card memory. The addition of 100words to the memory capacity will not only enhance the ease ofprogramming problems for the ENIAC but will also increase theover-all speed of computation by reducing the number of referencesto the slower access-time magnetic drum memory system.Magnetic memory devices have been under development in a numberof laboratories throughout the country for more than three years.At the Harvard Computation Laboratory magnetic shift registers thatuse rectangular hysteresis-loop magnetic materials have beendeveloped. Their new Mark IV Computer contains 200 words of thesemagnetic shift register memories. The Digital Computer Laboratoryof MIT, and more recently the Research Laboratories of RCA, haveinvestigated static magnetic memory systems of thecoincidence-current type.In November 1951 the Ballistics Research Laboratory of theAberdeen Proving Ground requested the delivery of a static magneticmemory system for the ENIAC. The time schedule implied that thesystem had to be designed from proven techniques, thus eliminatingthe possibility of extensive laboratory development. In addition,the peripheral electronics required for code conversion and controlimposed other conditions on the system that further limited thefreedom of design. One system that had already been demonstrated inour laboratory was well suited to the ENIAC requirements, andalthough not the optimum in magnetic memories, could be appliedimmediately to the problem. This system has the followingdistinctive characteristics:(1) It utlizes one magnetic core with two windings and onegermanium diode per bit of memory.(2) The magnetizing force applied to a core is always ofsufficient magnitude to switch the core, that is, the system is notamplitude-sensitive.(3) Information is stored in and extracted from the matrixmemory in parallel.(4) Read-out is inherently destructive, but the data isimmediately restored to the core matrix by the associatedelectronics.(5) No power is needed to hold information in the cores, andinformation is not lost in case of power failure.(6) It operates at pulse repetition rates from push button to125 kilocycles per second, therefore it can provide an excellentspeed match or buffer between systems.This paper will be presented in three parts:(1) A description of the basic memory matrix and a descriptionof how data is stored and extracted.(2) A review of the experimental results of a four by fourmatrix memory.(3) The system as designed for the ENIAC, and some of itsconstruction features. |
Starting Page | 213 |
Ending Page | 222 |
Page Count | 10 |
File Format | |
DOI | 10.1145/609784.609813 |
Language | English |
Publisher | Association for Computing Machinery (ACM) |
Publisher Date | 1952-05-02 |
Publisher Place | New York |
Access Restriction | Subscribed |
Content Type | Text |
Resource Type | Article |
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