NDLI: Multicore-aware hybrid code positioning to reduce worst-case execution time

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Content Provider	ACM Digital Library
Author	Ding, Yiqiang Zhang, Wei
Abstract	Unlike general-purpose programs, it is important to reduce the worst-case performance rather than the average-case performance for real-time systems. In this paper, based on a dual-core processor with a shared L2 cache, we propose a code positioning scheme that can reduce the worst-case execution time (WCET) for real-time threads by minimizing both the intra-thread and inter-thread instruction cache misses. Our experiments indicate that the proposed hybrid code positioning approach can effectively reduce the worst-case performance for real-time threads running on this dual-core processor.
Starting Page	1
Ending Page	8
Page Count	8
File Format	PDF
ISBN	9781605589213
DOI	10.1145/1739025.1739029
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-03-13
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multicore processors Wcet Real-time systems Code positioning
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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Multicore-aware hybrid code positioning to reduce worst-case execution time