NDLI: MIC acceleration of short-range molecular dynamics simulations

Please wait, while we are loading the content...

Automatic speculative parallelization of loops using polyhedral dependence analysis

MIC acceleration of short-range molecular dynamics simulations

Prius: a runtime for hybrid computing

Fast dynamic binary rewriting to support thread migration in shared-ISA asymmetric multicores

MIC acceleration of short-range molecular dynamics simulations

Content Provider	ACM Digital Library
Author	Wu, Qiang Yang, Canqun Xiao, Liquan Tang, Tao
Abstract	Heterogeneous systems containing accelerators such as GPUs or co-processors such as Intel MIC are becoming more prevalent due to their ability of exploiting large-scale parallelism in applications. In this paper, we have developed a hierarchical parallelization scheme for molecular dynamics simulations on CPU-MIC heterogeneous systems. The scheme exploits multi-level parallelism combining (1) task-level parallelism using a tightly-coupled division method, (2) thread-level parallelism employing spatial-decomposition through dynamically scheduled multi-threading, and (3) data-level parallelism via SIMD technology. By employing a hierarchy of parallelism with several optimization methods such as memory latency hiding and data pre-fetching, our MD code running on a CPU-MIC heterogeneous system (one 2.60GHZ eight-core Intel Xeon E5-2670 CPU and one 57-core Intel Knight Corner co-processor) achieves (1) multi-thread parallel efficiency of 72.4% for 57 threads on the co-processor with up to 7.62 times SIMD speedup on each core for the force computation task, and (2) up to 2.25 times speedup on the CPU-MIC system over the pure CPU system, which outperforms our previous work on a CPU-GPU (one NVIDIA Tesla M2050) platform. Our work shows that MD simulations can benefit enormously from the CPU-MIC heterogeneous platforms.
Starting Page	1
Ending Page	8
Page Count	8
File Format	PDF
ISBN	9781450319713
DOI	10.1145/2446920.2446922
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-02-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	High performance computing Heterogeneous computing Intel mic
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in