NDLI: Modeling and simulation to the design of ΣΔ fractional-N frequency synthesizer

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ATLAS: a chip-multiprocessor with transactional memory support

A non-intrusive isolation approach for soft cores

Bus access optimisation for FlexRay-based distributed embedded systems

Simulation-based reusable posynomial models for MOS transistor parameters

Synthesis of task and message activation models in real-time distributed automotive systems

Hard real-time reconfiguration port scheduling

Efficient high-performance ASIC implementation of JPEG-LS encoder

SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling

Microprocessors in the era of terascale integration

CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions

Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis

Assessing carbon nanotube bundle interconnect for future FPGA architectures

Low complexity LDPC code decoders for next generation standards

Using the inter- and intra-switch regularity in NoC switch testing

Fast memory footprint estimation based on maximal dependency vector calculation

Flexibility-oriented design methodology for reconfigurable ΔΣ modulators

DFM/DFY: should you trust the surgeon or the family doctor?

Automatic synthesis of compressor trees: reevaluating large counters

Applications for ubiquitous computing and communications

Timing simulation of interconnected AUTOSAR software-components

Dynamic learning based scan chain diagnosis

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation

An efficient code compression technique using application-aware bitmask and dictionary selection methods

An algorithm to minimize leakage through simultaneous input vector control and circuit modification

Hardware scheduling support in SMP architectures

Cost-aware capacity optimization in dynamic multi-hop WSNs

Emerging solutions technology and business views for the ubiquitous communication

Development of on board, highly flexible, Galileo signal generator ASIC

Testable design for advanced serial-link transceivers

Heterogeneous systems on chip and systems in package

Engineering trust with semantic guardians

Adaptive power management in energy harvesting systems

Instruction trace compression for rapid instruction cache simulation

Power supply and power management in Ubicom

From algorithm to first 3.5G call in record time: a novel system design approach based on virtual prototyping and its consequences for interdisciplinary system design teams

Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs

A multi-core debug platform for NoC-based systems

Compositional specification of behavioral semantics

Life begins at 65: unless you are mixed signal?

Routing table minimization for irregular mesh NoCs

Testing in the year 2020

Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM

WAVSTAN: waveform based variational static timing analysis

CARAT: a toolkit for design and performance analysis of component-based embedded systems

Dynamic reconfiguration in sensor networks with regenerative energy sources

System level assessment of an optical NoC in an MPSoC platform

The methodological and technological dimensions of technology transfer for embedded systems in aeronautics and space

Energy evaluation of software implementations of block ciphers under memory constraints

Utilization of SECDED for soft error and variation-induced defect tolerance in caches

A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states

pFFT in FastMaxwell: a fast impedance extraction solver for 3D conductor structures over substrate

A future of customizable processors: are we there yet?

Fast and accurate routing demand estimation for efficient routability-driven placement

Industrial applications

Flying embedded: the industrial scene and challenges for embedded systems in aeronautics and space

Compact hardware design of Whirlpool hashing core

Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs

A new hybrid solution to boost SAT solver performance

Polynomial-time subgraph enumeration for automated instruction set extension

Computing synchronizer failure probabilities

Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application

Development and industrialisation

Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system

Soft error rate analysis for sequential circuits

Design challenges at 65nm and beyond

Instruction-set customization for real-time embedded systems

Fast positive-real balanced truncation of symmetric systems using cross Riccati equations

Accurate temperature-dependent integrated circuit leakage power estimation is easy

Towards total open source in aeronautics and space?

A tiny and efficient wireless ad-hoc protocol for low-cost sensor networks

A framework for system reliability analysis considering both system error tolerance and component test quality

Use of statistical timing analysis on real designs

Accounting for cache-related preemption delay in dynamic priority schedulability analysis

Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks

Architectural leakage-aware management of partitioned scratchpad memories

Keynote address: Challenges of digital consumer and mobile SoC's: more Moore possible?

A dynamically adaptive DSP for heterogeneous reconfigurable platforms

Unknown blocking scheme for low control data volume and high observability

A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors

Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming

An ILP formulation for system-level application mapping on network processor architectures

An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs

Improve CAM power efficiency using decoupled match line scheme

Optimized integration of test compression and sharing for SOC testing

A symbolic methodology for the verification of analog and mixed signal designs

Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL

Two-level microprocessor-accelerator partitioning

Non-fractional parallelism in LDPC decoder implementations

Toward a scalable test methodology for 2D-mesh Network-on-Chips

Mapping multi-dimensional signals into hierarchical memory organizations

Experimental validation of a tuning algorithm for high-speed filters

Area optimization of multi-cycle operators in high-level synthesis

FPGA-based networking systems for high data-rate and reliable in-vehicle communications

Diagnosis, modeling and tolerance of scan chain hold-time violations

A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays

Optimizing instruction-set extensible processors under data bandwidth constraints

Understanding voltage variations in chip multiprocessors using a distributed power-delivery network

A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method

Design methods for security and trust

New safety critical radio altimeter for airbus and related design flow

Method for reducing jitter in multi-gigahertz ATE

CATS: cycle accurate transaction-driven simulation with multiple processor simulators

Stochastic modeling and optimization for robust power management in a partially observable system

Efficient code density through look-up table compression

Portable multimedia SoC design: a global challenge

Error rate reduction in DNA self-assembly by non-constant monomer concentrations and profiling

Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support

Performance analysis of multimedia applications using correlated streams

Congestion-controlled best-effort communication for networks-on-chip

Event driven data processing architecture

Rapid and accurate latch characterization via direct Newton solution of setup/hold times

Modeling and simulation alternatives for the design of networked embedded systems

Dynamic power management under uncertain information

Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture

An area optimized reconfigurable encryptor for AES-Rijndael

Transient fault prediction based on anomalies in processor events

Estimating functional coverage in bounded model checking

Optimization-based wideband basis functions for efficient interconnect extraction

Yield-aware placement optimization

An efficient polynomial multiplier in $GF(2^{m})$ and its application to ECC designs

Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry

QuteSAT: a robust circuit-based SAT solver for complex circuit structure

Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems

Layout-aware gate duplication and buffer insertion

Clock domain crossing fault model and coverage metric for validation of SoC design

Mapping the physical layer of radio standards to multiprocessor architectures

Verification-guided soft error resilience

The ARTEMIS cross-domain architecture for embedded systems

A novel technique to use scratch-pad memory for stack management

Random sampling of moment graph: a stochastic Krylov-reduction algorithm

Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling

Scalable reconfigurable channel decoder architecture for future wireless handsets

Experimental evaluation of protections against laser-induced faults and consequences on fault modeling

A novel criticality computation method in statistical timing analysis

Energy-efficient real-time task scheduling with task rejection

Impact of process variations on multicore performance symmetry

Memory bank aware dynamic loop scheduling

Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore's law?

An 0.9 × 1.2", low power, energy-harvesting system with custom multi-channel communication interface

Test cost reduction for SoC using a combined approach to test data compression and test scheduling

Design closure driven delay relaxation based on convex cost network flow

An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection

A smooth refinement flow for co-designing HW and SW threads

Improving utilization of reconfigurable resources using two dimensional compaction

Cyclostationary feature detection on a tiled-SoC

A sophisticated memory test engine for LCD display drivers

Efficient nonlinear distortion analysis of RF circuits

A calculator for Pareto points

Design space exploration of partially re-configurable embedded processors

Minimum-energy LDPC decoder for real-time mobile application

Remote testing and diagnosis of System-on-Chips using network management frameworks

The impact of loop unrolling on controller delay in high level synthesis

Design of high-resolution MOSFET-only pipelined ADCs with digital calibration

Data-flow transformations using Taylor expansion diagrams

Low-g accelerometer fast prototyping for automotive applications

On test generation by input cube avoidance

Reversible circuit technology mapping from non-reversible specifications

Resource prediction for media stream decoding

Process variation tolerant low power DCT architecture

Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding

Introducing new verification methods into a company's design flow: an industrial user's point of view

Re-configuration of sub-blocks for effective application of time domain tests

A one-shot configurable-cache tuner for improved energy and performance

Efficient and scalable compiler-directed energy optimization for realtime applications

Microarchitectural support for program code integrity monitoring in application-specific instruction set processors

What if you could design tomorrow's system today?

Design and DfT of a high-speed area-efficient embedded asynchronous FIFO

Incremental ABV for functional validation of TL-to-RTL design refinement

Simulation platform for UHF RFID

Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip

Reconfigurable system-on-chip data processing units for space imaging instruments

Temperature and voltage aware timing analysis: application to voltage drops

Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns

Very wide register: an asymmetric register file organization for low power embedded processors

Analytical router modeling for networks-on-chip performance analysis

Performance aware secure code partitioning

Low-cost protection for SER upsets and silicon defects

Abstraction and refinement techniques in automated design debugging

Thermally robust clocking schemes for 3D integrated circuits

Microarchitecture floorplanning for sub-threshold leakage reduction

Flexible hardware reduction for elliptic curve cryptography in $GF(2^{m})$

A two-tone test method for continuous-time adaptive equalizers

Boosting the role of inductive invariants in model checking

DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems

Self-heating-aware optimal wire sizing under Elmore delay model

Fast statistical circuit analysis with finite-point based transistor model

Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow

A low-SER efficient core processor architecture for future technologies

HW/SW implementation from abstract architecture models

Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison

Statistical model order reduction for interconnect circuits considering spatial correlations

Maximum circuit activity estimation using pseudo-boolean satisfiability

A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems

Evaluation of design for reliability techniques in embedded flash memories

Efficient computation of the worst-delay corner

Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systems

Temperature aware task scheduling in MPSoCs

System level clock tree synthesis for power optimization

Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio

High-level test synthesis for delay fault testability

Interactive presentation: A coefficient optimization and architecture selection tool for ΣΔ modulators in MATLAB

Speeding up SystemC simulation through process splitting

Low-power warp processor for power efficient high-performance embedded systems

Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter

Formal verification of a pervasive interconnect bus system in a high-performance microprocessor

Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis

Modeling and simulation to the design of ΣΔ fractional-N frequency synthesizer

Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor

Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture

Clock-frequency assignment for multiple clock domain systems-on-a-chip

A new technique for characterization of digital-to-analog converters in high-speed systems

Automatic application specific floating-point unit generation

Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508

Slow write driver faults in 65nm SRAM technology: analysis and March test solution

Distributed power-management techniques for wireless network video systems

Register pointer architecture for efficient embedded processors

Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction

Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms

An ADC-BiST scheme using sequential code analysis

Design fault directed test generation for microprocessor validation

Interactive presentation: Peripheral-conscious scheduling on energy minimization for weakly hard real-time systems

Interactive presentation: Soft-core processor customization using the design of experiments paradigm

Test quality analysis and improvement for an embedded asynchronous FIFO

Efficient testbench code synthesis for a hardware emulator system

Tool-support for the analysis of hybrid systems and models

Enabling certification for dynamic partial reconfiguration using a minimal flow

Accurate timing analysis using SAT and pattern-dependent delay models

Lightweight middleware for seamless HW-SW interoperability, with application to wireless sensor networks

Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory

Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform

Energy and execution time analysis of a software-based trusted platform module

Working with process variation aware caches

Interactive presentation: Automatic hardware synthesis from specifications: a case study

Double-via-driven standard cell library design

Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware

Worst-case design and margin for embedded SRAM

Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs

Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations

Interactive presentation: Statistical simulation of high-frequency bipolar circuits

An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip

Accurate and scalable reliability analysis of logic circuits

Task scheduling for reliable cache architectures of multiprocessor systems

A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing

Optimization of the "FOCUS" Inband-FEC architecture for 10-Gbps SDH/SONET optical communication channels

Reduction of detected acceptable faults for yield improvement via error-tolerance

Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems

Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip

Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices

Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm

Interactive presentation: Low cost debug architecture using lossy compression for silicon debug

Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitations

Interactive presentation: System level power optimization of Sigma-Delta modulator

Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture

Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs

Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP

Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system

Interactive presentation: On power-profiling and pattern generation for power-safe scan tests

Interactive presentation: Improving the fault tolerance of nanometric PLA designs

Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search

Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique

Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance

Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC

Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs

Interactive presentation: Implementation of a transaction level assertion framework in SystemC

Interactive presentation: Automatic model generation for black box real-time systems

Identification of process/design issues during 0.18 µm technology qualification for space application

Interactive presentation: A middleware-centric design flow for networked embedded systems

Interactive presentation: PowerQuest: trace driven data mining for power optimization

Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor

Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining

Interactive presentation: Pulse propagation for the detection of small delay defects

Interactive presentation: A process splitting transformation for Kahn process networks

Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems

Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA

Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's

Interactive presentation: Process tolerant β-ratio modulation for ultra-dynamic voltage scaling

Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver

Interactive presentation: An FPGA implementation of decision tree classification

Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers

Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns

Interactive presentation: Reliability-aware system synthesis

Interactive presentation: Towards a methodology for the quantitative evaluation of automotive architectures

Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits

Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy

Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor

Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions

Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics

Interactive presentation: Functional and timing validation of partially bypassed processor pipelines

Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits

Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling

Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model

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