NDLI: Considering process variations during system-level power analysis

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Considering process variations during system-level power analysis

Content Provider	ACM Digital Library
Author	Raghunathan, Anand Lahiri, Kanishka Dey, Sujit Chandra, Saumya
Abstract	Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various design techniques to address process variations at the mask, circuit, and logic levels. However, as the magnitude of process variations increases, their effects will need to be addressed earlier in the design cycle.In this paper, we propose techniques for accurately and efficiently incorporating the effects of process variations into system-level power estimation tools. To motivate our work, we first study the impact of process variations on the power consumption of an example System-on-Chip (SoC). We consider simple extensions of current approaches to system-level power estimation (spreadsheet-based and simulation-based power estimation), and demonstrate their limitations in performing variation-aware power estimation. We propose a system-level power estimation methodology that can accurately and efficiently analyze the impact of process variations on SoC power. The proposed methodology combines efficient trace-based analysis, power-state based leakage modeling, and Monte Carlo sampling. The key benefit of the proposed methodology is that it captures the necessary inter-dependencies while avoiding iterative system-level simulation. Our implementation of the proposed techniques within an in-house system-level power estimation framework indicates 2-5 orders of magnitude efficiency gains, with negligible loss in accuracy, compared to direct Monte Carlo techniques that require iterative system simulation.
Starting Page	342
Ending Page	345
Page Count	4
File Format	PDF
ISBN	1595934626
DOI	10.1145/1165573.1165654
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-10-04
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Low power design Power estimation Power analysis Process variations System-on-chip
Content Type	Text
Resource Type	Article

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