NDLI: Maximizing the performance of irregular applications on multithreaded, NUMA systems

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Maximizing the performance of irregular applications on multithreaded, NUMA systems

Content Provider	ACM Digital Library
Author	Cong, Guojing Wen, Huifang
Abstract	In modern shared-memory systems, the communication latency and available resources for a group of logical processors are determined by their relative position in the hierarchy of chips, cores, and hardware threads. Thus the performance of multithreaded applications varies with the mapping of software threads to logical processors. In our study we observe huge variation in application performance under different mappings. Moreover, applications with irregular access patterns perform poorly under the default mapping. We maximize application performance by balancing communication overhead and available resources. Remote access overhead in irregular applications dominates execution time and can not be reduced by mapping alone on NUMA systems when the logical processors span multiple chips. In addition to new data replication and distribution optimizations, we improve geographical locality by matching access pattern to the data layout. We further propose a locality-centric optimization for simultaneously reducing remote accesses and improving cache performance. Our approach achieves better performance than prior NUMA-specific techniques.
Starting Page	1
Ending Page	8
Page Count	8
File Format	PDF
ISBN	9781450325035
DOI	10.1145/2535753.2535756
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-11-17
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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