NDLI: Architectural support for the efficient generation of code for horizontal architectures

Please wait, while we are loading the content...

Hardware/software cooperation in the iAPX-432

Hardware/software tradeoffs for increased performance

Coding guidelines for pipelined processors

An overview of the mesa processor architecture

The operating system and language support features of the BELLMACTM-32 microprocessor.

The 801 minicomputer

Register allocation for free: The C machine stack cache

An architectural alternative to optimizing compilers

Fast procedure calls

Systematic protection mechanism design

On a general property of memory mapping tables

An experiment to improve operand addressing

Compiler chip: A hardware implementation of compiler

Architectural support for the efficient generation of code for horizontal architectures

Guidelines for creating a debuggable processor

Hardware support for memory protection: Capability implementations

Supporting ada memory management in the iAPX-432

Direct execution of lisp on a list_directed architecture

Some requirements for architectural support of software debugging

The effect of the PDP-11 architecture on code generation for chill

Empirical analysis of the mesa instruction set

An analysis of a mesa instruction set using dynamic instruction frequencies

A case study of VAX-11 instruction set usage for compiler execution

Firmware structure and architectural support for monitors, vertical migration and user microprogramming

Heart: An operating system nucleus machine implemented by firmware

A multi-microprocessor architecture with hardware support for communication and scheduling

Architectural support for the efficient generation of code for horizontal architectures

Content Provider	ACM Digital Library
Author	Rau, B. R. Greenawalt, E. M. Glaeser, C. D.
Abstract	Horizontal architectures, such as the CDC Advanced Flexible Processor [I] and the FPS APi20-B [2}, consist of a number of resources that can operate in parallel, each of which is controlled by a field in the wide instruction word. Such architectures have been developed to perform high speed scientific computations at a modest cost: Figure 1 displays those characteristics of horizontal architectures that are germane to the issues discussed in this paper. The simultaneous requirements of high performance and low cost lead to an architecture consisting of multiple pipelined processing elements (PEs) such as adders and multipliers, a memory (which for scheduling purposes may be viewed as yet another PE with two operations: a READ and a WRITE), and an interconnect which ties them all together. The interconnect allows the result of one operation to be directly routed to another PE as one of the inputs for an operation that is to be performed there. The required memory bandwidth is reduced since temporary values need not be written to and read from the memory. The final aspect of horizontal processors that is of interest is that their program memories emit wide instructions which synchronously specify the actions of the multiple and possibly dissimilar PEs. The program memory is sequenced by a conventional sequencer that assumes sequential flow of control unless a branch is explicitly specified. As a consequence of the simplicity of such an architecture, it is inexpensive relative to the potential performance of the multiple pipelined PEs. However, if this potential performance is to be realized, the multiple resources of a horizontal processor must be scheduled effectively. The scheduling task for conventional horizontal processors is quite complex and the construction of highly optimizing compilers for them is a difficult and expensiw3 project. The polycyclic architecture [3- 6] is a horizontal architecture with architectural support for the scheduling task. The cause of the complexity involved in scheduling conventional horizontal processors and the manner in which the polycyclic architecture addresses this issue are outlined in this paper.
Starting Page	96
Ending Page	99
Page Count	4
File Format	PDF
ISBN	0897910664
DOI	10.1145/800050.801832
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1982-03-01
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in