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Memory organization with multi-pattern parallel accesses

Content Provider	ACM Digital Library
Author	Vitkovski, Arseni Kuzmanov, Georgi Gaydadjiev, Georgi
Abstract	We propose an interleaved memory organization supporting multi-pattern parallel accesses in two-dimensional (2D) addressing space. Our proposal targets computing systems with high memory bandwidth demands such as vector processors, multimedia accelerators, etc. We substantially extend prior research on interleaved memory organizations introducing 2D-strided accesses along with additional parameters, which define a large variety of 2D data patterns. The proposed scheme guarantees minimum memory latency and efficient bandwidth utilization for arbitrary configuration parameters of the data pattern. We provide mathematical descriptions and proofs of correctness for the proposed addressing schemes. The design complexity and the critical paths are evaluated using technology independent resource counts and confirm the scalability of the proposal. Hardware synthesis results for 90nm CMOS technology suggest that throughputs in the range between 44 and 1182 Gbit/s can be obtained at the cost of 26-212 Kgates for configurations of 2x2 32-bit up to 8x8 64-bit memory modules.
Starting Page	1420
Ending Page	1425
Page Count	6
File Format	PDF
ISBN	9783981080131
DOI	10.1145/1403375.1403719
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-03-10
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	High bandwidth Conflict-free access Parallel memories Multi-pattern access
Content Type	Text
Resource Type	Article

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