NDLI: Safe automatic flight back and landing of aircraft flight reconfiguration function (FRF)

Please wait, while we are loading the content...

Designing micro/nano systems for a safer and healthier tomorrow

Cycle-approximate retargetable performance estimation at the transaction level

Tailored solutions for safety-installations in the Loetschberg tunnel: a project with importance for the trans-European rail traffic

A reconfigurable application specific instruction set processor for convolutional and turbo decoding in a SDR environment

Optimal high-resolution spectral analyzer

Quantitative evaluation in embedded system design: trends in modeling and analysis techniques

A framework of stochastic power management using hidden Markov model

Parametric throughput analysis of synchronous data flow graphs

Sizing rules for bipolar analog circuit design

Symbolic reliability analysis and optimization of ECU networks

Analysis of the test data volume reduction benefit of modular SOC testing

Performance analysis of SoC architectures based on latency-rate servers

Resilient dynamic power management under uncertainty

Built-in clock skew system for on-line debug and repair

Temperature-aware scheduling and assignment for hard real-time applications on MPSoCs

Periodic steady-state analysis augmented with design equality constraints

Mapping semantics of CORBA IDL and GIOP to open core protocol for portability and interoperability of SDR waveform components

Guiding circuit level fault-tolerance design with statistical methods

Software for wireless networked embedded systems

Fine-grained supply gating through hypergraph partitioning and Shannon decomposition for active power reduction

Physical architectures of automotive systems

A mutation model for the SystemC TLM 2.0 communication interfaces

Efficient representation and analysis of power grids

Optimizing near-ML MIMO detector for SDR baseband on parallel programmable architectures

Low power Illinois scan architecture for simultaneous power and test data volume reduction

A game-theoretic approach to real-time system testing

Caution ahead: the road to design and manufacturing at 32 and 22 nm

Fault clustering in deep-submicron CMOS processes

Software components for reliable automotive systems

Model-based-design is nice but...

A simulation methodology for worst-case response time estimation of distributed real-time systems

An efficient method for chip-level statistical capacitance extraction considering process variations with spatial correlation

Generic multi-phase software-pipelined Partial-FFT on instruction-level-parallel architectures and SDR baseband applications

On modeling and testing of lithography related open faults in nano-CMOS circuits

Computation of buffer capacities for throughput constrained and data dependent inter-task communication

ARTEMIS and ENIAC joint undertakings: a new approach to conduct

Methods, tools and standards for the analysis, evaluation and design of modern automotive architectures

Random stimulus generation using entropy and XOR constraints

Comparison of opamp-based and comparator-based delta-sigma modulation

A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers

Test strategies for low power devices

Thermal balancing policy for streaming computing on multiprocessor architectures

Run-time system for an extensible embedded processor with dynamic instruction set

Test instrumentation for a laser scanning localization technique for analysis of high speed DRAM devices

The future car: technology, methods and tools: panel session

Improving constant-coefficient multiplier verification by partial product identification

Novel pin assignment algorithms for components with very high pin counts

A triple-mode reconfigurable sigma-delta modulator for multi-standard wireless applications

CASP: concurrent autonomous chip self-test using stored test patterns

Logical reliability of interacting real-time tasks

Quantitative productivity measurement in IC design

Implications of technology trends on system dependability

Subsystem exchange in a concurrent design process environment

Process variation tolerant pipeline design through a placement-aware multiple voltage island design style

Compositional, dynamic cache management for embedded chip multiprocessors

Design guidelines for metallic-carbon-nanotube-tolerant digital logic circuits

Improvements in polynomial-time feasibility testing for EDF

Simultaneous FU and register binding based on network flow method

VLSI implementation of SISO arithmetic decoders for joint source channel coding

Specification and design considerations for reliable embedded systems

Reliable services in an imperfect world

Video processing requirements on SoC infrastructures

Incremental criticality and yield gradients

Efficient software architecture for IPSec acceleration using a programmable security processor

A bridging fault model where undetectable faults imply logic redundancy

Hiding cache miss penalty using priority-based execution for embedded processors

Transparent reconfigurable acceleration for heterogeneous embedded applications

Dependability for high-tech systems: an industry-as-laboratory approach

User-aware dynamic task allocation in networks-on-chip

Variable latency speculative addition: a new paradigm for arithmetic circuit design

Defeating classical hardware countermeasures: a new processing for side channel analysis

Automated trace signals identification and state restoration for improving observability in post-silicon validation

Advanced analog filters for telecommunications

High-level modelling and exploration of coarse-grained re-configurable architectures

Automated dynamic throughput-constrained structural-level pipelining in streaming applications

Dependable embedded systems special day panel: issues and challenges in dependable embedded systems

Multicast parallel pipeline router architecture for network-on-chip

Memory organization with multi-pattern parallel accesses

Implementation of parallel LFSR-based applications on an adaptive DSP featuring a pipelined configurable Gate Array

Digital bit stream jitter testing using jitter expansion

Retargetable code optimization for predicated execution

Hot topic: 3D integration or how to scale in the 21st century

Perspective on embedded systems: challenges, solutions and research priorities

A method for the efficient development of timed and untimed transaction-level models of systems-on-chip

On the verification of high-order constraint compliance in IC design

Using reconfigurable logic to optimise GPU memory accesses

A general method to evaluate RF BIST techniques based on non-parametric density estimation

Quantitative evaluation in embedded system design: validation of multiprocessor multithreaded architectures

Harvesting wasted heat in a microprocessor using thermoelectric generators: modeling, analysis and measurement

Introducing preemptive scheduling in abstract RTOS models using result oriented modeling

Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density

Verification of temporal properties in automotive embedded software

Test-architecture optimization and test scheduling for SOCs with core-level expansion of compressed test patterns

Slack allocation based co-synthesis and optimization of bus and memory architectures for MPSoCs

Robust and low complexity rate control for solar powered sensors

Analysis and optimization of the recessed probe launch for high frequency measurements of PCB interconnects

A formal approach to the protocol converter problem

Analysis of oscillator injection locking by harmonic balance method

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications

A delay-efficient radiation-hard digital design approach using CWSP elements

A scalable algorithmic framework for row-based power-gating

Efficient design validation based on cultural algorithms

High-frequency mutual impedance extraction of VLSI interconnects in the presence of a multi-layer conducting substrate

Vectorization of Reed solomon decoding and mapping on the EVP

Scan chain organization for embedded diagnosis

Modeling event stream hierarchies with hierarchical event models

Energy efficient and high speed on-chip ternary bus

Signal probability based statistical timing analysis

SPARE: a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction

A novel recursive algorithm for bit-efficient realization of arbitrary length inverse modified cosine transforms

Optimal margin computation for at-speed test

Constraint refinement for online verifiable cross-layer system adaptation

MCjammer: adaptive verification for multi-core designs

A novel technique for improving temperature independency of ring-ADC

A coarse-grained array based baseband processor for 100Mbps+ software defined radio

A practical approach for reconciling high and predictable performance in non-regular parallel programs

Harnessing horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency

A mapping framework for guided design space exploration of heterogeneous MP-SoCs

Improved visibility in one-to-many trace concretization

A generic standard cell design methodology for differential circuit styles

Low-noise sigma-delta capacitance-to-digital converter for Sub-pF capacitive sensors with integrated dielectric loss measurement

Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology

Scheduling of fault-tolerant embedded systems with soft and hard timing constraints

Globally optimized robust systems to overcome scaled CMOS reliability challenges

Cooperative safety: a combination of multiple technologies

Optimal MTCMOS reactivation under power supply noise and performance constraints

Comparison of memory write policies for NoC based multicore cache coherent systems

Quantified synthesis of reversible logic

A dual-priority real-time multiprocessor system on FPGA for automotive applications

A variation aware high level synthesis framework

Error detection/correction in DNA algorithmic self-assembly

Synthesis of fault-tolerant embedded systems

Memory technology for extended large-scale integration in future electronics applications

Latch modeling for statistical timing analysis

Operating system controlled processor-memory bus encryption

Layout-aware, IR-drop tolerant transition fault pattern generation

Instruction cache energy saving through compiler way-placement

Automatic selection of application-specific reconfigurable processor extensions

Minimizing virtual channel buffer for routers in on-chip communication architectures

Improving synthesis of compressor trees on FPGAs via integer linear programming

Power balanced gates insensitive to routing capacitance mismatch

Functional self-testing for bus-based symmetric multiprocessors

Emerging yield and reliability challenges in nanometer CMOS technologies

Scalable architecture for on-chip neural network training using swarm intelligence

Towards trojan-free trusted ICs: problem analysis and detection scheme

Variation tolerant NoC design by means of self-calibrating links

CATCH: a mechanism for dynamically detecting Cache-Content-Duplication and its application to instruction caches

GMDS: hardware implementation of novel real output queuing architecture

A same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution

Programming shared memory multiprocessors with deterministic message-passing concurrency: compiling SHIM to Pthreads

Integrating RTL IPs into TLM designs through automatic transactor generation

Industrial IP integration flows based on IP-XACT™ standards

Cost-and power optimized FPGA based system integration: methodologies and integration of a low-power capacity-based measurement application on Xilinx FPGAs

Diagnostic analysis of static errors in multi-step analog to digital converters

Quantitative evaluation in embedded system design: predicting battery lifetime in mobile devices

An efficient solar energy harvester for wireless sensor nodes

SystemC-based modelling, seamless refinement, and synthesis of a JPEG 2000 decoder

A new approach for combining yield and performance in behavioural models for analogue integrated circuits

A novel approach for EMI design of power electronics

An novel methodology for reducing SoC test data volume on FPGA-based testers

Run-time spatial mapping of streaming applications to a heterogeneous multi-processor system-on-chip (MPSoC)

Energy aware dynamic voltage and frequency selection for real-time systems with energy harvesting

On automated trigger event generation in post-silicon validation

Cache aware mapping of streaming applications on a multiprocessor system-on-chip

Model checking of analog systems using an analog specification language

Hot wire anemometric MEMS sensor for water flow monitoring

Towards fault tolerant parallel prefix adders in nanoelectronic systems

Coarse-grain MTCMOS sleep transistor sizing using delay budgeting

Algorithms for maximum satisfiability using unsatisfiable cores

ETBR: extended truncated balanced realization method for on-chip power grid network analysis

A case study in reliability-aware design: a resilient LDPC code decoder

State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores

Semantics for model-based validation of continuous/discrete systems

Task scheduling with configuration prefetching and anti-fragmentation techniques on dynamically reconfigurable systems

A current source model for CMOS logic cells considering multiple input switching and stack effect

Transistor-specific delay modeling for SSTA

Definition and SIMD implementation of a multi-processing architecture approach on FPGA

Resistive bridging fault simulation of industrial circuits

Adaptive scheduling and voltage scaling for multiprocessor real-time applications with non-deterministic workload

Efficient implementation of native software simulation for MPSoC

An analog on-chip adaptive body bias calibration for reducing mismatches in transistor pairs

Scenario-based fixed-point data format refinement to enable energy-scalable software defined radios

Exact and approximate task assignment algorithms for pipelined software synthesis

Instruction set extension exploration in multiple-issue architecture

Impact of leakage current on data retention of RF-powered devices during amplitude-modulation-based communication

Efficient symbolic simulation of low level software

Layout level timing optimization by leveraging active area dependent mobility of strained-silicon devices

Calibration of integrated CMOS hall sensors using coil-on-chip in ATE environment

A low-cost concurrent error detection technique for processor control logic

Tool support for incremental failure mode and effects analysis of component-based systems

Software protection mechanisms for dependable systems

System performance optimization methodology for Infineon's 32-bit automotive microcontroller architecture

A single-supply true voltage level shifter

Serialized asynchronous links for NoC

Adaptive simulation for single-electron devices

An application-based EDF scheduler for OSEK/VDX

EPIC: ending piracy of integrated circuits

Temperature-aware voltage selection for energy optimization

Memory-aware NoC exploration and design

Conditional partial order graphs and dynamically reconfigurable control synthesis

An efficient FPGA implementation of principle component analysis based network intrusion detection system

Multi-vector tests: a path to perfect error-rate testing

Effective loop partitioning and scheduling under memory and register dual constraints

An optimized message passing framework for parallel implementation of signal processing applications

An open-loop flow control scheme based on the accurate global information of on-chip communication

An adaptable FPGA-based system for regular expression matching

On analysis and synthesis of (n, k)-non-linear feedback shift registers

Theoretical and practical aspects of Iddq Settling: impact on measurement timing and quality

Novel front-end circuit architectures for integrated bio-electronic interfaces

Intelligent merging online task placement algorithm for partial reconfigurable systems

Wrapper and TAM co-optimization for reuse of SoC functional interconnects

BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs

Magellan: a search and machine learning-based framework for fast multi-core design space exploration and optimization

Front end device for content networking

A design-for-diagnosis technique for SRAM write drivers

Modularity vs. reusability: code generation from synchronous block diagrams

Design flow for embedded FPGAs based on a flexible architecture template

Practical implementation of a network analyzer for analog BIST applications

Temperature control of high-performance multi-core platforms using convex optimization

Modeling refining heterogeneous systems with SystemC-AMS: application to WSN

Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments

Architecture exploration of NAND flash-based multimedia card

Dynamic voltage scaling of supply and body bias exploiting software runtime distribution

Dynamic round-robin task scheduling to reduce cache misses for embedded systems

Synthesizing synchronous elastic flow networks

A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking

In-band cross-trigger event transmission for transaction-based debug

Bandwidth-centric optimisation for area-constrained links with crosstalk avoidance methods

Automated testability enhancements for logic brick libraries

Using UML as front-end for heterogeneous software code generation strategies

Fast analog circuit synthesis using sensitivity based near neighbor searches

Current source based standard cell model for accurate signal integrity and timing analysis

Physically-aware N-detect test pattern selection

Simulation-directed invariant mining for software verification

Integrated approach to energy harvester mixed technology modelling and performance optimisation

Instruction re-encoding facilitating dense embedded code

Accuracy-adaptive simulation of transaction level models

Completeness in SMT-based BMC for software programs

Exploiting correlation kernels for efficient handling of intra-die spatial correlation, with application to statistical timing

A programmable and low-EMI integrated half-bridge driver in BCD technology

Approximate logic circuits for low overhead, non-intrusive concurrent error detection

Compositional design of isochronous systems

Clock distribution scheme using coplanar transmission lines

OS-based sensor node platform and energy estimation model for health-care wireless sensor networks

Time properties of the BuST protocol under the NPA budget allocation scheme

A fast approximation algorithm for MIN-ONE SAT

iFill: an impact-oriented X-filling method for shift- and capture-power reduction in at-speed scan-based testing

Comparison of Boolean satisfiability encodings on FPGA detailed routing problems

FPGA design for algebraic tori-based public-key cryptography

Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor

de Bruijn graph as a low latency scalable architecture for energy efficient massive NoCs

Developing mesochronous synchronizers to enable 3D NoCs

Process variation aware issue queue design

Power aware reconfigurable multiprocessor for elliptic curve cryptography

Variable delay of multi-gigahertz digital signals for deskew and jitter-injection test applications

ezRealtime: a domain-specific modeling tool for embedded hard real-time software synthesis

Improving the efficiency of run time reconfigurable devices by configuration locking

Spatial correlation extraction via random field simulation and production chip performance regression

Zero-efficient buffer design for reliable network-on-chip in tiled chip-multi-processor

Deep submicron interconnect timing model with quadratic random variable analysis

Adaptive filesystem compression for embedded systems

Logic synthesis with nanowire crossbar: reality check and standard cell-based integration

A methodology for improving software design lifecycle in embedded control systems

Wire sizing alternative: an uniform dual-rail routing architecture

An efficient algorithm for free resources management on the FPGA

Partially redundant logic detection using symbolic equivalence checking in reversible and irreversible logic circuits

Merged computation for Whirlpool hashing

Finding the worst voltage violation in multi-domain clock gated power network

Structural synthesis of four-quadrant multiplier based on hierarchical topology

Performance-constrained different cell count minimization for continuously-sized circuits

TinyTimber, reactive objects in C for real-time embedded systems

Source-level timing annotation and simulation for a heterogeneous multiprocessor

A system architecture for reconfigurable trusted platforms

A virtual prototype for Bluetooth over ultra wide band system level design

Test scheduling for wafer-level test-during-burn-in of core-based SoCs

Dynamic task allocation strategies in MPSoC for soft real-time applications

Safe automatic flight back and landing of aircraft flight reconfiguration function (FRF)

Automatic generation of complex properties for hardware designs

Re-examining the use of network-on-chip as test access mechanism

CARbridge, reduction of system complexity by standardisation of the system-basis-chips for automotive applications

Mixed-signal design space exploration of time-interleaved A/D converters for ultra-wide band applications

PWM-based test stimuli generation for BIST of high resolution ΣΔ ADCs

Safe automatic flight back and landing of aircraft flight reconfiguration function (FRF)

Content Provider	ACM Digital Library
Author	Herrería García, Juan Alberto
Abstract	SOFIA (Safe Automatic Flight Back and Landing of Aircraft) project is a response to the challenge of developing concepts and techniques enabling the safe and automatic return to ground in the event of hostile actions. Activities in this sense have been started in the framework of the SAFEE SP3 (Secure Aircraft in the Future European Environment Sub-Project 3) project. SOFIA project is proposed as the continuation of the SAFEE works on FRF (Flight Reconfiguration Function), the system to automatically return the aircraft to ground. SOFIA will design architectures for integrating the FRF system into several typologies of avionics for civil transport aircraft; development of one of this architectures; validation, following E-OCVM (European Operational Concept Validation Methodology) of the FRF concept and the means to integrate it in the current ATM (Air Traffic Management); safety assessment of FRF at aircraft and operational (ATC-Air Traffic Control) levels. The SOFIA product is the FRF system that will take the control of the aircraft and will manage to safely return it to ground under a security emergency (e.g. hijacking), disabling the control and command of the aircraft from the cockpit. This means to create and execute a new flight plan towards a secure airport and landing the aircraft at it. The flight plan can be generated in ground (ATC), or in a military airplane and transmitted to the aircraft, or created autonomously at the FRF.
Starting Page	280
Ending Page	283
Page Count	4
File Format	PDF
ISBN	9783981080131
DOI	10.1145/1403375.1403443
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-03-10
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in