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| Content Provider | ACM Digital Library |
|---|---|
| Author | Eom, Young-Sik Jhon, Chu-Shik Jhang, Seong-Tae |
| Abstract | In Chip Multi-Processors (CMPs) with private L2 caches, to combine the strengths of private and shared caches, private caches can share capacity through spilling replaced blocks to other private caches. However, indiscriminate spilling can make the capacity problem worse and influence performance negatively. This paper proposes throttling capacity sharing (TCS) for effective capacity sharing. TCS determines whether to spill a replaced block by predicting its reuse possibility based on stack distance. We evaluate the performance improvement of TCS in a 4 core system. TCS improves weighted speedup on average by 54.64%, 5.34% and 7.21% compared to no spilling, Cooperative Caching (CC) with best spill probability and Dynamic Spill-Receive (DSR), respectively. |
| Starting Page | 20 |
| Ending Page | 24 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781450310871 |
| DOI | 10.1145/2103380.2103385 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2011-11-02 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Capacity sharing Cooperative caching Private l2 cache Chip multi-processors |
| Content Type | Text |
| Resource Type | Article |
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