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| Content Provider | ACM Digital Library |
|---|---|
| Author | Vangal, Sriram Mattson, Timothy G. Haas, Werner Riepen, Michael Dighe, Saurabh Lehnig, Thomas Kennedy, Patrick Howard, Jason Borkar, Nitin Ruhl, Greg Brett, Paul |
| Abstract | The number of cores integrated onto a single die is expected to climb steadily in the foreseeable future. This move to many-core chips is driven by a need to optimize performance per watt. How best to connect these cores and how to program the resulting many-core processor, however, is an open research question. Designs vary from GPUs to cache-coherent shared memory multiprocessors to pure distributed memory chips. The 48-core SCC processor reported in this paper is an intermediate case, sharing traits of message passing and shared memory architectures. The hardware has been described elsewhere. In this paper, we describe the programmer's view of this chip. In particular we describe RCCE: the native message passing model created for the SCC processor. |
| Starting Page | 1 |
| Ending Page | 11 |
| Page Count | 11 |
| File Format | |
| ISBN | 9781424475599 |
| DOI | 10.1109/SC.2010.53 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2010-11-13 |
| Access Restriction | Subscribed |
| Content Type | Text |
| Resource Type | Article |
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