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Evaluation of Hardware Synchronization Support of the SCC Many-Core Processor
| Content Provider | Semantic Scholar |
|---|---|
| Author | Reble, Pablo Lankes, Stefan Zeitz, Florian Bemmerl, Thomas |
| Copyright Year | 2012 |
| Abstract | The integration of many cores per chip will lead to inefficiency of traditional multi-processor techniques. In particular, a hardware cache coherency protocol includes performance and hardware overhead, so that for a growing number of cores the coherence wall problem will become more serious. The Single-chip Cloud Computer (SCC) is a recent research processor of a Cluster-on-Chip architecture, that waives a hardware-based coherency and possesses a network on chip technology. An attractive alternative to enable shared memory programming models on future many-core systems is the introduction of a softwareoriented coherency. Any software based approach, such as shared virtual memory (SVM), will need fast synchronization methods. The assumption is that hardware support is essential to achieve this performance. In this paper we will study and evaluate this hypothesis. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://eecourses.technion.ac.il/048879/papers-2014/HWsyncSCC.pdf |
| Alternate Webpage(s) | https://www.usenix.org/system/files/conference/hotpar12/hotpar12-final9.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
