NDLI: Split tiling for GPUs: automatic parallelization using trapezoidal tiles

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Split tiling for GPUs: automatic parallelization using trapezoidal tiles

Content Provider	ACM Digital Library
Author	Verdoolaege, Sven Grosser, Tobias Ramanujam, J. Cohen, Albert Sadayappan, P. Kelly, Paul H. J.
Abstract	Tiling is a key technique to enhance data reuse. For computations structured as one sequential outer "time" loop enclosing a set of parallel inner loops, tiling only the parallel inner loops may not enable enough data reuse in the cache. Tiling the inner loops along with the outer time loop enhances data locality but may require other transformations like loop skewing that inhibit inter-tile parallelism. One approach to tiling that enhances data locality without inhibiting inter-tile parallelism is split tiling, where tiles are subdivided into a sequence of trapezoidal computation steps. In this paper, we develop an approach to generate split tiled code for GPUs in the PPCG polyhedral code generator. We propose a generic algorithm to calculate index-set splitting that enables us to perform tiling for locality and synchronization avoidance, while simultaneously maintaining parallelism, without the need for skewing or redundant computations. Our algorithm performs split tiling for an arbitrary number of dimensions and without the need to construct any large integer linear program. The method and its implementation are evaluated on standard stencil kernels and compared with a state-of-the-art polyhedral compiler and with a domain-specific stencil compiler, both targeting CUDA GPUs.
Starting Page	24
Ending Page	31
Page Count	8
File Format	PDF
ISBN	9781450320177
DOI	10.1145/2458523.2458526
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-03-16
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Code generation Polyhedral model Index set splitting Stencil Loop transformations Time tiling Cuda Gpgpu Compilers
Content Type	Text
Resource Type	Article

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