NDLI: Leveraging Silicon-Photonic NoC for Designing Scalable GPUs

Please wait, while we are loading the content...

Streaming Task Parallelism

Automatic Parallelization of Kernels in Shared-Memory Multi-GPU Nodes

PaCMap: Topology Mapping of Unstructured Communication Patterns onto Non-contiguous Allocations

Locality-Driven Dynamic GPU Cache Bypassing

Automatic Selection of Sparse Matrix Representation on GPUs

Datacenter Efficiency: What's Next?

Towards Lightweight and Swift Storage Resource Management in Big Data Cloud Era

MODESTO: Data-centric Analytic Optimization of Complex Stencil Programs on Heterogeneous Architectures

GreenPar: Scheduling Parallel High Performance Applications in Green Datacenters

History-Assisted Adaptive-Granularity Caches (HAAG\$) for High Performance 3D DRAM Architectures

Automatically Scalable Computation

Mower: A New Design for Non-blocking Misprediction Recovery

PALMOS: A Transparent, Multi-tasking Acceleration Layer for Parallel Heterogeneous Systems

CSR5: An Efficient Storage Format for Cross-Platform Sparse Matrix-Vector Multiplication

Automatic Energy Efficient Parallelization of Uniform Dependence Computations

COMPASS: A Framework for Automated Performance Modeling and Prediction

A Stall-Aware Warp Scheduling for Dynamically Optimizing Thread-level Parallelism in GPGPUs

Unique Worker model for OpenMP

SemCache++: Semantics-Aware Caching for Efficient Multi-GPU Offloading

Fine-Grained Synchronizations and Dataflow Programming on GPUs

Hadoop+: Modeling and Evaluating the Heterogeneity for MapReduce Applications in Heterogeneous Clusters

FAST: A Fast Stencil Autotuning Framework Based On An Optimal-solution Space Model

Underprovisioning the Grid Power Infrastructure for Green Datacenters

Real-Time In-Memory Checkpointing for Future Hybrid Memory Systems

zFENCE: Data-less Coherence for Efficient Fences

A Nested Partitioning Algorithm for Adaptive Meshes on Heterogeneous Clusters

Optimistic Delinearization of Parametrically Sized Arrays

ASPaS: A Framework for Automatic SIMDization of Parallel Sorting on x86-based Many-core Processors

Composing Algorithmic Skeletons to Express High-Performance Scientific Applications

PeerWave: Exploiting Wavefront Parallelism on GPUs with Peer-SM Synchronization

Exploiting Process Imbalance to Improve MPI Collective Operations in Hierarchical Systems

DaCache: Memory Divergence-Aware GPU Cache Management

Enabling and Exploiting Flexible Task Assignment on GPU through SM-Centric Program Transformations

Active Access: A Mechanism for High-Performance Distributed Data-Centric Computations

Parameterized Diamond Tiling for Stencil Computations with Chapel parallel iterators

Building Fuel Powered Supercomputing Data Center at Low Cost

Leveraging Silicon-Photonic NoC for Designing Scalable GPUs

Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures

DASX: Hardware Accelerator for Software Data Structures

Optimizing Overlapped Memory Accesses in User-directed Vectorization

STAPL-RTS: An Application Driven Runtime System

Exascaling Your Library: Will Your Implementation Meet Your Expectations?

Quantifying Performance Bottlenecks of Stencil Computations Using the Execution-Cache-Memory Model

Leveraging Silicon-Photonic NoC for Designing Scalable GPUs

Content Provider	ACM Digital Library
Author	Chen, Chao Ziabari, Amir Kavyan Kavyan Joshi, Ajay Ubal, Rafael Kaeli, David Abellán, Jose L.
Abstract	Silicon-photonic link technology promises to satisfy the growing need for high bandwidth, low-latency and energy-efficient network-on-chip (NoC) architectures. While silicon-photonic NoC designs have been extensively studied for future many-core systems, their use in massively-threaded GPUs has received little attention to date. In this paper, we first analyze an electrical NoC which connects different cache levels (L1 to L2) in a contemporary GPU memory hierarchy. Evaluating workloads from the AMD SDK run on the Multi2sim GPU simulator finds that, apart from limits in memory bandwidth, an electrical NoC can significantly hamper performance and impede scalability, especially as the number of compute units grows in future GPU systems. To address this issue, we advocate using silicon-photonic link technology for on-chip communication in GPUs, and we present the first GPU-specific analysis of a cost-effective hybrid photonic crossbar NoC. Our baseline is based on an AMD Southern Islands GPU with 32 compute units (CUs) and we compare this design to our proposed hybrid silicon-photonic NoC. Our proposed photonic hybrid NoC increases performance by up to 6 x (2.7 x on average) and reduces the $energy-delay^{2}$ product $(ED^{2}P)$ by up to 99% (79% on average) as compared to conventional electrical crossbars. For future GPU systems, we study an electrical 2D-mesh topology since it scales better than an electrical crossbar. For a 128-CU GPU, the proposed hybrid silicon-photonic NoC can improve performance by up to 1.9 x (43% on average) and achieve up to 62% reduction in $ED^{2}P$ (3% on average) in comparison to mesh design with best performance.
Starting Page	273
Ending Page	282
Page Count	10
File Format	PDF
ISBN	9781450335591
DOI	10.1145/2751205.2751229
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-06-08
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Gpus Photonics technology Network-on-chip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Highly Scalable Butterfly-Based Photonic Network-on-Chip

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures

Photonic NoC for DMA Communications in Chip Multiprocessors

BLOCON: a bufferless photonic Clos Network-on-Chip architecture

Optical burst switching for many-core processor-to-memory photonic networks

Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration

Scalable single-photon detection on a photonic chip

Invited paper photonic network-on-chip architecture using 3d integration.

Leveraging Silicon-Photonic NoC for Designing Scalable GPUs

Similar Documents

A Highly Scalable Butterfly-Based Photonic Network-on-Chip

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures

Photonic NoC for DMA Communications in Chip Multiprocessors

BLOCON: a bufferless photonic Clos Network-on-Chip architecture

Optical burst switching for many-core processor-to-memory photonic networks

Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration

Scalable single-photon detection on a photonic chip

Invited paper photonic network-on-chip architecture using 3d integration.

Leveraging Silicon-Photonic NoC for Designing Scalable GPUs