NDLI: Distributed replay protocol for distributed uniprocessors

Please wait, while we are loading the content...

High performance supercomputers: should the individual processor be more than a brick?

Distributed replay protocol for distributed uniprocessors

Characterizing and improving the use of demand-fetched caches in GPUs

UniFI: leveraging non-volatile memories for a unified fault tolerance and idle power management technique

Overcoming single-thread performance hurdles in the core fusion reconfigurable multicore architecture

HiRe: using hint & release to improve synchronization of speculative threads

Sparse matrix-vector multiply on the HICAMP architecture

Blue Gene/Q: design for sustained multi-petaflop computing

An analysis of computational workloads for the ORNL Jaguar system

Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities

Hardware support for enforcing isolation in lock-based parallel programs

SnuCL: an OpenCL framework for heterogeneous CPU/GPU clusters

One stone two birds: synchronization relaxation and redundancy removal in GPU-CPU translation

Fault tolerant preconditioned conjugate gradient for sparse linear system solution

CVP: an energy-efficient indirect branch prediction with compiler-guided value pattern

Enhancing the performance of assisted execution runtime systems through hardware/software techniques

On the communication complexity of 3D FFTs and its implications for Exascale

Unified memory optimizing architecture: memory subsystem control with a unified predictor

High-performance code generation for stencil computations on GPU architectures

clSpMV: A Cross-Platform OpenCL SpMV Framework on GPUs

Fast loop-level data dependence profiling

Data-driven fault tolerance for work stealing computations

Congestion avoidance on manycore high performance computing systems

CATS: cache aware task-stealing based on online profiling in multi-socket multi-core architectures

Composable, non-blocking collective operations on power7 IH

Locality & utility co-optimization for practical capacity management of shared last level caches

An efficient work-distribution strategy for gridding radio-telescope data on GPUs

Enabling and scaling matrix computations on heterogeneous multi-core and multi-GPU systems

Apricot: an optimizing compiler and productivity tool for x86-compatible many-core coprocessors

Fault resilience of the algebraic multi-grid solver

Channel borrowing: an energy-efficient nanophotonic crossbar architecture with light-weight arbitration

CRQ-based fair scheduling on composable multicore architectures

Collective algorithms for sub-communicators

Exploiting communication and packaging locality for cost-effective large scale networks

GPU merge path: a GPU merging algorithm

An optimized large-scale hybrid DGEMM design for CPUs and ATI GPUs

Quantifying the effectiveness of load balance algorithms

Space-round tradeoffs for MapReduce computations

Distributed replay protocol for distributed uniprocessors

Content Provider	ACM Digital Library
Author	Mao, Mengjie An, Hong Sun, Tao Zhou, Wei Deng, Bobin Wei, Xuechao Han, Wenting
Abstract	Data speculation technique has been heavily exploited in various scenarios of architecture design. It bridges the time or space gap between data producer and data consumer, which gives opportunities to processors to gain significant speedups. However, large instruction windows, deep pipeline and increasing latency of on-chip communication make data misspeculation very expensive in modern processors. This paper proposes a Distributed Replay Protocol(DRP) that addresses data misspeculation in a distributed uniprocessor, named TFlex. The partition feature of distributed uniprocessors aggravates the penalty of data misspeculation. After detecting misspeculation, DRP avoids squashing pipeline; on the contrary, it retains all instructions in the window and selectively replays the instructions that depend on the misspeculative data. As one possible use of DRP, We apply it to recovery from data dependence speculation. We also summarize the challenges of implementing selective replay mechanism on distributed uniprocessors, and then come up with two variations of DRP to effectively solve these challenges. The evaluation results show that without data speculation, DRP achieves 99% of the performance of perfect memory disambiguation. It speeds up diverse applications over baseline TFlex(with a state-of-art data dependence predictor) by a geometric mean of 24%.
Starting Page	3
Ending Page	14
Page Count	12
File Format	PDF
ISBN	9781450313162
DOI	10.1145/2304576.2304580
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-06-25
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Data misspeculation Selective re-execution Selective recovery Distributed uniprocessors Selective replay
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Scalable selective re-execution for EDGE architectures

Scalable Selective Re-Execution for EDGE Architectures (2004)

Scalable selective re-execution for EDGE architectures (CARN, Vol. 32, Issue. 5)

Scalable selective re-execution for EDGE architectures (SIGP, Vol. 39, Issue. 11)

Scalable selective re-execution for EDGE architectures (OPSR, Vol. 38, Issue. 5)

A Distributed Execution Replay Facility for Chorus a Distributed Execution Replay Facility for Chorus

Optimizing Caching DSM for Distributed Software Speculation

Practical Selective Replay for Reduced-Tag Schedulers

Transparent control independence (TCI)

Distributed replay protocol for distributed uniprocessors

Similar Documents

Scalable selective re-execution for EDGE architectures

Scalable Selective Re-Execution for EDGE Architectures (2004)

Scalable selective re-execution for EDGE architectures (CARN, Vol. 32, Issue. 5)

Scalable selective re-execution for EDGE architectures (SIGP, Vol. 39, Issue. 11)

Scalable selective re-execution for EDGE architectures (OPSR, Vol. 38, Issue. 5)

A Distributed Execution Replay Facility for Chorus a Distributed Execution Replay Facility for Chorus

Optimizing Caching DSM for Distributed Software Speculation

Practical Selective Replay for Reduced-Tag Schedulers

Transparent control independence (TCI)

Distributed replay protocol for distributed uniprocessors