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Power-efficient breadth-first search with DRAM row buffer locality-aware address mapping
| Content Provider | ACM Digital Library |
|---|---|
| Author | Ono, Takatsugu Imamura, Satoshi Sasaki, Hiroshi Yasui, Yuichiro Fujisawa, Katsuki Inoue, Koji |
| Abstract | Graph analysis applications have been widely used in real services such as road-traffic analysis and social network services. Breadth-first search (BFS) is one of the most representative algorithms for such applications; therefore, many researchers have tuned it to maximize performance. On the other hand, owing to the strict power constraints of modern HPC systems, it is necessary to improve power efficiency (i.e., performance per watt) when executing BFS. In this work, we focus on the power efficiency of DRAM and investigate the memory access pattern of a state-of-the-art BFS implementation using a cycle-accurate processor simulator. The results reveal that the conventional address mapping schemes of modern memory controllers do not efficiently exploit row buffers in DRAM. Thus, we propose a new scheme called per-row channel interleaving and improve the DRAM power efficiency by 30.3% compared to a conventional scheme for a certain simulator setting. Moreover, we demonstrate that this proposed scheme is effective for various configurations of memory controllers. |
| Starting Page | 17 |
| Ending Page | 24 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781509038800 |
| DOI | 10.1109/HPGDMP.2016.7 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2016-11-13 |
| Access Restriction | Subscribed |
| Subject Keyword | Address mapping scheme Breadth-first search Row buffer Dram Power efficiency |
| Content Type | Text |
| Resource Type | Article |
