NDLI: Recursive circuit clustering for minimum delay and area

Content Provider	ACM Digital Library
Author	Dehkordi, Mehrdad Eslami Brown, Stephen D.
Abstract	We present an effective recursive algorithm for circuit clustering for delay and area minimization, which is applicable to FPGAs. At the highest level of clustering, the circuit is clustered using a modified single-level clustering algorithm. A cluster to netlist transformation technique is proposed, which converts each cluster into a new subcircuit. The algorithm then continues recursively by clustering the generated subcircuits into further levels of clusters. To reduce the amount of node duplication and the number of clusters at each level of clustering, we propose a node removal algorithm based on the node slack along with a simple cluster-packing algorithm. Experimental results on the two-level clustering problem using Quartus Design System from Altera show that our algorithm achieves, on average, 7.3% more delay reduction when compared to the latest published work on the problem. Also total FPGA compile time reported by Quartus is reduced by 36%.
Starting Page	242
Ending Page	242
Page Count	1
File Format	PDF
ISBN	158113651X
DOI	10.1145/611817.611865
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-02-23
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Recursive circuit clustering for minimum delay and area