NDLI: Circuit clustering for delay minimization under area and pin constraints

Content Provider	IEEE Xplore Digital Library
Author	Honghua Yang Wong, D.F.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci., Texas Univ., Austin, TX, USA (Honghua Yang; Wong, D.F.)
Abstract	We consider the problem of circuit partitioning for multiple-chip implementation. One motivation for studying this problem is the current needs of good partitioning tools for implementing a circuit on multiple FPGA chips. We allow duplication of logic gates as if would reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to both area and pin constraints on each chip, using the general delay model. We develop a repeated network cut technique for finding a cluster that is bounded by both area and pin constraints. Our algorithm achieves optimal delay under either the area constraint only or the pin constraint only. Under both area and pin constraints, our algorithm achieves optimal delay in most cases. We outline the condition under which the non-optimality occurs and show that the condition occurs rarely in practice. We tested our algorithm on a set of benchmark circuits and consistently obtained optimal or near-optimal delays.<>
Starting Page	65
Ending Page	70
File Size	669081
Page Count	6
File Format	PDF
ISBN	0818670398
DOI	10.1109/EDTC.1995.470418
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-03-06
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Minimization Clustering algorithms Logic gates Logic circuits Circuit testing Delay effects Partitioning algorithms Algorithm design and analysis Field programmable gate arrays Benchmark testing
Content Type	Text
Resource Type	Article

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