NDLI: Scale-out processors

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RAIDR: Retention-Aware Intelligent DRAM Refresh

Simultaneous branch and warp interweaving for sustained GPU performance

Branch regulation: low-overhead protection from code reuse attacks

Tolerating process variations in nanophotonic on-chip networks

Watchdog: hardware for safe and secure manual memory management and full memory safety

Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures

Euripus: a flexible unified hardware memory checkpointing accelerator for bidirectional-debugging and reliability

Reducing memory reference energy with opportunistic virtual caching

Setting an error detection infrastructure with low cost acoustic wave detectors

A case for exploiting subarray-level parallelism (SALP) in DRAM

Physically addressed queueing (PAQ): improving parallelism in solid state disks

Can traditional programming bridge the Ninja performance gap for parallel computing applications?

Configurable fine-grain protection for multicore processor virtualization

Managing distributed ups energy for effective power capping in data centers

End-to-end sequential consistency

PARDIS: a programmable memory controller for the DDRx interfacing standards

CAPRI: prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

Side-channel vulnerability factor: a metric for measuring information leakage

A micro-architectural analysis of switched photonic multi-chip interconnects

RADISH: always-on sound and complete Ra Detection in Software and Hardware

The yin and yang of power and performance for asymmetric hardware and managed software

VRSync: characterizing and eliminating synchronization-induced voltage emergencies in many-core processors

A first-order mechanistic model for architectural vulnerability factor

Improving writeback efficiency with decoupled last-write prediction

Viper: virtual pipelines for enhanced reliability

PreSET: improving performance of phase change memories by exploiting asymmetry in write times

Staged memory scheduling: achieving high performance and scalability in heterogeneous systems

Harmony: collection and analysis of parallel block vectors

Revisiting hardware-assisted page walks for virtualized systems

Scale-out processors

BlockChop: dynamic squash elimination for hybrid processor architecture

BOOM: enabling mobile memory based low-power server DIMMs

iGPU: exception support and speculative execution on GPUs

TimeWarp: rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks

Enhancing effective throughput for transmission line-based bus

LOT-ECC: localized and tiered reliability mechanisms for commodity memory systems

FLEXclusion: balancing cache capacity and on-chip bandwidth via flexible exclusion

A defect-tolerant accelerator for emerging high-performance applications

Buffer-on-board memory systems

Probabilistic shared cache management (PriSM)

iSwitch: coordinating and optimizing renewable energy powered server clusters

The dynamic granularity memory system

Towards energy-proportional datacenter memory with mobile DRAM

Boosting mobile GPU performance with a decoupled access/execute fragment processor

Inspection resistant memory: architectural support for security from physical examination

A case for random shortcut topologies for HPC interconnects

Scale-out processors

Content Provider	ACM Digital Library
Author	Jevdjic, Djordje Grot, Boris Ferdman, Michael Kocberber, Onur Idgunji, Sachin Lotfi-Kamran, Pejman Adileh, Almutaz Volos, Stavros Falsafi, Babak Ozer, Emre Picorel, Javier
Abstract	Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by on-die caches of existing server chips. Large caches reduce the die area available for cores and lower performance through long access latency when instructions are fetched. Performance on scale-out workloads is maximized through a modestly-sized last-level cache that captures the instruction footprint at the lowest possible access latency. In this work, we introduce a methodology for designing scalable and efficient scale-out server processors. Based on a metric of performance-density, we facilitate the design of optimal multi-core configurations, called pods. Each pod is a complete server that tightly couples a number of cores to a small last-level cache using a fast interconnect. Replicating the pod to fill the die area yields processors which have optimal performance density, leading to maximum per-chip throughput. Moreover, as each pod is a stand-alone server, scale-out processors avoid the expense of global (i.e., inter-pod) interconnect and coherence. These features synergistically maximize throughput, lower design complexity, and improve technology scalability. In 20nm technology, scale-out chips improve throughput by 5x-6.5x over conventional and by 1.6x-1.9x over emerging tiled organizations.
Starting Page	500
Ending Page	511
Page Count	12
File Format	PDF
ISBN	9781450316422
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-06-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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