NDLI: BOOM: enabling mobile memory based low-power server DIMMs

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RAIDR: Retention-Aware Intelligent DRAM Refresh

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Tolerating process variations in nanophotonic on-chip networks

Watchdog: hardware for safe and secure manual memory management and full memory safety

Scheduling heterogeneous multi-cores through Performance Impact Estimation (PIE)

Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures

Euripus: a flexible unified hardware memory checkpointing accelerator for bidirectional-debugging and reliability

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PARDIS: a programmable memory controller for the DDRx interfacing standards

CAPRI: prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

Side-channel vulnerability factor: a metric for measuring information leakage

A micro-architectural analysis of switched photonic multi-chip interconnects

RADISH: always-on sound and complete Ra Detection in Software and Hardware

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VRSync: characterizing and eliminating synchronization-induced voltage emergencies in many-core processors

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Viper: virtual pipelines for enhanced reliability

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Staged memory scheduling: achieving high performance and scalability in heterogeneous systems

Harmony: collection and analysis of parallel block vectors

Revisiting hardware-assisted page walks for virtualized systems

Scale-out processors

BlockChop: dynamic squash elimination for hybrid processor architecture

BOOM: enabling mobile memory based low-power server DIMMs

iGPU: exception support and speculative execution on GPUs

TimeWarp: rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks

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LOT-ECC: localized and tiered reliability mechanisms for commodity memory systems

FLEXclusion: balancing cache capacity and on-chip bandwidth via flexible exclusion

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BOOM: enabling mobile memory based low-power server DIMMs

Content Provider	ACM Digital Library
Author	Muralimanohar, Naveen Ranganathan, Parthasarathy Yoon, Doe Hyun Chang, Jichuan
Abstract	To address the real-time processing needs of large and growing amounts of data, modern software increasingly uses main memory as the primary data store for critical information. This trend creates a new emphasis on high-capacity, high-bandwidth, and high-reliability main memory systems. Conventional and recently-proposed server memory techniques can satisfy these requirements, but at the cost of significantly increased memory power, a key constraint for future memory systems. In this paper, we exploit the low-power nature of another high volume memory component---mobile DRAM---while improving its bandwidth and reliability shortcomings with a new DIMM architecture. We propose Buffered Output On Module (BOOM) that buffers the data outputs from multiple ranks of low-frequency mobile DRAM devices, which in aggregation provide high bandwidth and achieve chipkill-correct or even stronger reliability. Our evaluation shws that BOOM can reduce main memory power by more than 73% relative to the baseline chipkill system, while improving average performance by 5% and providing strong reliability. For memory-intensive applications, BOOM can improve performance by 30--40%.
Starting Page	25
Ending Page	36
Page Count	12
File Format	PDF
ISBN	9781450316422
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-06-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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