NDLI: Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs

Please wait, while we are loading the content...

$R^{2}Cache:$ reliability-aware reconfigurable last-level cache architecture for multi-cores

How to improve the space utilization of dedup-based PCM storage devices?

A tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones

Design methodologies for securing cyber-physical systems

LearnLoc: a framework for smart indoor localization with embedded mobile devices

Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs

Analysis and optimization of soft error tolerance strategies for real-time systems

Improved hard real-time scheduling of CSDF-modeled streaming applications

dsReliM: power-constrained reliability management in dark-silicon many-core chips under process variations

Hardware synthesis from a recursive functional language

Power-awareness and smart-resource management in embedded computing systems

seBoost: selective boosting for heterogeneous manycores

An online wear state monitoring methodology for off-the-shelf embedded processors

Big/little deep neural network for ultra low power inference

An approximate compressor for wearable biomedical healthcare monitoring systems

Computer security by hardware-intrinsic authentication

Energy efficient FFT implementation through stage skipping and merging

Fast parallel application and multiprocessor design space exploration from sequential code

Run-DMC: runtime dynamic heterogeneous multicore performance and power estimation for energy efficiency

Transparent and portable agent based task migration for data-flow applications on multi-tiled architectures

A parallelizable approach for mining likely invariants

Completeness bounds and sequentialization for model checking of interacting firmware and hardware

Fault injection acceleration by architectural importance sampling

The shift to multicores in real-time and safety-critical systems

Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs

Content Provider	ACM Digital Library
Author	Vogel, Pirmin Benini, Luca Marongiu, Andrea
Abstract	While high-end heterogeneous systems are increasingly supporting heterogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the embedded domain still lack basic features like virtual memory support for accelerators. As opposed to simply passing virtual address pointers, explicit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance. In this work, we present a mixed hardware/software solution to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded systems-on-chip (SoCs). Based on an input/output translation lookaside buffer (IOTLB), efficiently managed by a kernel-level driver module running on the host, our solution features a considerably lower design complexity compared to conventional input/output memory management units. Using our evaluation platform based on the Xilinx Zynq-7000 SoC with a many-core accelerator implemented in the programmable logic, we demonstrate the effectiveness of our solution and the benefits of virtual memory support for embedded heterogeneous SoCs.
Starting Page	45
Ending Page	54
Page Count	10
File Format	PDF
ISBN	9781467383219
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-10-04
Access Restriction	Subscribed
Subject Keyword	Programmable many-core accelerators Virtual shared memory Heterogeneous embedded systems on chip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs

An Evaluation of Memory Sharing Performance for Heterogeneous Embedded SoCs with Many-Core Accelerators

Revisiting shared virtual memory systems for non-coherent memory-coupled cores

Task mapping techniques for embedded many-core SoCs

A Virtualization Framework for IOMMU-less Many-Core Accelerators

Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs

Enabling zero-copy OpenMP offloading on the PULP many-core accelerator

A static task mapping algorithm with dynamic task switching for embedded many-core SoCs

A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory

Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs

Similar Documents

Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs

An Evaluation of Memory Sharing Performance for Heterogeneous Embedded SoCs with Many-Core Accelerators

Revisiting shared virtual memory systems for non-coherent memory-coupled cores

Task mapping techniques for embedded many-core SoCs

A Virtualization Framework for IOMMU-less Many-Core Accelerators

Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs

Enabling zero-copy OpenMP offloading on the PULP many-core accelerator

A static task mapping algorithm with dynamic task switching for embedded many-core SoCs

A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory

Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs