NDLI: BB-GC: Basic-Block Level Garbage Collection

Please wait, while we are loading the content...

Effective Lower Bounding Techniques for Pseudo-Boolean Optimization

Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver

A Faster Counterexample Minimization Algorithm Based on Refutation Analysis

Functional Coverage Driven Test Generation for Validation of Pipelined Processors

Pueblo: A Modern Pseudo-Boolean SAT Solver

Space-Efficient Bounded Model Checking

Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking

A Model-Based Approach for Executable Specifications on Reconfigurable Hardware

The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application

A SoC Design Methodology Involving a UML 2.0 Profile for SystemC

UML 2.0 Profile for Embedded System Design

UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design

Design Refinement for Efficient Cluste ing of Objects in Embedded Systems

Challenges in Embedded Memory Design and Test

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures

Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture

Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler

Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications

An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation

Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design

Statistical Timing Analysis using Levelized Covariance Propagation

A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching

Modeling and Propagation of Noisy Waveforms in Static Timing Analysis

A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs

Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation

Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip

FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations

Nonuniform Banking for Reducing Memory Energy Consumption

Systematic Analysis of Active Clock Deskewing Systems Using Control Theory

Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip

Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory

UML 2.0 - Overview and Perspectives in SoC Design

Why Systems-on-Chip Needs More UML like a Hole in the Head

Integrating UML into SoC Design Process

Rapid Generation of Thermal-Safe Test Schedules

Simultaneous Reduction of Dynamic and Static Power in Scan Structures

A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs

New Schemes for Self-Testing RAM

At-Speed Logic BIST for IP Cores

Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems

Locality-Aware Process Scheduling for Embedded MPSoCs

A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms

Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems

System Synthesis for Networks of Programmable Blocks

Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks

Synchronization Processor Synthesis for Latency Insensitive Systems

Thermal-Aware Task Allocation and Scheduling for Embedded Systems

An Improved Multi-Level Framework for Force-Directed Placement

Bright-Field AAPSM Conflict Detection and Correction

Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules

TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform

Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric

Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies

Compositional Memory Systems for Multimedia Communicating Tasks

Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes

A New System Design Methodology for Wire Pipelined SoC

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck

Is there a Market for SystemC Tools?

Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model

Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction

Stochastic Power Grid Analysis Considering Process Variations

Buffer Insertion Considering Process Variation

EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation

Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis

Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions

Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization

Implicit and Exact Path Delay Fault Grading in Sequential Circuits

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs

Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation

The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits

Diagnostic and Detection Fault Collapsing for Multiple Output Circuits

Framework for Fault Analysis and Test Generation in DRAMs

Mutation Sampling Technique for the Generation of Structural Test Data

Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing

BB-GC: Basic-Block Level Garbage Collection

Fine Grain QoS Control for Multimedia Application Software

Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development

galsC: A Language for Event-Driven Embedded Systems

Compiler-Directed Instruction Duplication for Soft Error Detection

OS Debugging Method Using a Lightweight Virtual Machine Monitor

Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications

Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits

Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces

Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework

CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming

A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling

New Perspectives and Opportunities From the Wild West of Microelectronic Biochips

Verification of Embedded Memory Systems using Efficient Memory Modeling

An Efficient Sequential SAT Solver With Improved Search Strategies

Considering Circuit Observability Don't Cares in CNF Satisfiability

Integration, Verification and Layout of a Complex Multimedia SOC

JPEG, MPEG-4, and H.264 Codec IP Development

SOC Testing Methodology and Practice

Evolutionary Optimization in Code-Based Test Compression

Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application

Hybrid BIST Based on Repeating Sequences and Cluster Analysis

C Compiler Retargeting Based on Instruction Semantics Models

A Constraint Network Based Approach to Memory Layout Optimization

Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access

Structural Testing Based on Minimum Kernels

An Application-Specific Design Methodology for STbus Crossbar Generation

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips

Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration

Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips

Quantum Circuit Simplification Using Templates

Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths

CMOS-Based Biosensor Arrays

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips

A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks

ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement

Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis

Reliability-Centric High-Level Synthesis

PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors

Concurrent Error Detection in Asynchronous Burst-Mode Controllers

Reliable System Specification for Self-Checking Data-Paths

Evaluation of Error-Resilience for Reliable Compression of Test Data

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Automatic Formal Verification of Fused-Multiply-Add FPUs

Refinement Maps for Efficient Verification of Processor Models

Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code

Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission

An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types

RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power

eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical Detection

Cantilever-Based Biosensors in CMOS Technology

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in