NDLI: Functional Coverage Driven Test Generation for Validation of Pipelined Processors

Content Provider	ACM Digital Library
Author	Dutt, Nikil Mishra, Prabhat
Abstract	Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validation of such systems is the lack of a suitable functional coverage metric. This paper presents a functional coverage based test generation technique for pipelined architectures. The proposed methodology makes three important contributions. First, a general graph-theoretic model is developed that can capture the structure and behavior (instruction-set) of a wide variety of pipelined processors. Second, we propose a functional fault model that is used to define the functional coverage for pipelined architectures. Finally, test generation procedures are presented that accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. Our experimental results on two pipelined processor models demonstrate that the number of test programs generated by our approach to obtain a fault coverage is an order of magnitude less than those generated by traditional random or constrained-random test generation techniques.
Starting Page	678
Ending Page	683
Page Count	6
File Format	PDF
ISBN	0769522882
ISSN	15301591
DOI	10.1109/DATE.2005.162
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-03-07
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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Functional Coverage Driven Test Generation for Validation of Pipelined Processors