NDLI: A complexity separation between the cache-coherent and distributed shared memory models

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A complexity separation between the cache-coherent and distributed shared memory models

Content Provider	ACM Digital Library
Author	Golab, Wojciech
Abstract	We consider asynchronous multiprocessor systems where processes communicate by accessing shared memory. Exchange of information among processes in such a multiprocessor necessitates costly memory accesses called remote memory references (RMRs), which generate communication on the interconnect joining processors and main memory. In this paper we compare two popular shared memory architecture models, namely the ca che-coherent (CC) and distributed shared memory (DSM) models, in terms of their power for solving synchronization problems efficiently with respect to RMRs. The particular problem we consider entails one process sending a "signal" to a subset of other processes. We show that a variant of this problem can be solved very efficiently with respect to RMRs in the CC model, but not so in the DSM model, even when we consider amortized RMR complexity. To our knowledge, this is the first separation in terms of amortized RMR complexity between the CC and DSM models. It is also the first separation in terms of RMR complexity (for asynchronous systems) that does not rely in any way on wait-freedom---the requirement that a process makes progress in a bounded number of its own steps.
Starting Page	109
Ending Page	118
Page Count	10
File Format	PDF
ISBN	9781450307192
DOI	10.1145/1993806.1993822
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-06-06
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Shared memory models
Content Type	Text
Resource Type	Article

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