NDLI: Integrated temporal and spatial scheduling for extended operand clustered VLIW processors

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Integrated temporal and spatial scheduling for extended operand clustered VLIW processors

Content Provider	ACM Digital Library
Author	Nagpal, Rahul Srikant, Y. N.
Abstract	Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The consequence is the emergence of architectures having many interconnected clusters each with a separate register file and a few functional units. Among the many inter-cluster communication models proposed, the extended operand model extends some of operand fields of instruction with a cluster specifier and allows an instruction to read some of the operands from other clusters without any extra cost.Scheduling for clustered processors involves spatial concerns (where to schedule) as well as temporal concerns (when to schedule). A scheduler is responsible for resolving the conflicting requirements of aggressively exploiting the parallelism offered by hardware and limiting the communication among clusters to available slots. This paper proposes an integrated spatial and temporal scheduling algorithm for extended operand clustered VLIW processors and evaluates its effectiveness in improving the run time performance of the code without code size penalty.
Starting Page	457
Ending Page	470
Page Count	14
File Format	PDF
ISBN	1581137419
DOI	10.1145/977091.977155
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-04-14
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Spatial scheduling Temporal scheduling Clustered vliw processors
Content Type	Text
Resource Type	Article

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