NDLI: Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM

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Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM

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Freecursive ORAM: [Nearly] Free Recursion and Integrity Verification for Position-based Oblivious RAM

Content Provider	ACM Digital Library
Author	van Dijk, Marten Devadas, Srinivas Kwon, Albert Fletcher, Christopher W. Ren, Ling
Abstract	Oblivious RAM (ORAM) is a cryptographic primitive that hides memory access patterns as seen by untrusted storage. Recently, ORAM has been architected into secure processors. A big challenge for hardware ORAM schemes is how to efficiently manage the Position Map (PosMap), a central component in modern ORAM algorithms. Implemented naively, the PosMap causes ORAM to be fundamentally unscalable in terms of on-chip area. On the other hand, a technique called Recursive ORAM fixes the area problem yet significantly increases ORAM's performance overhead. To address this challenge, we propose three new mechanisms. We propose a new ORAM structure called the PosMap Lookaside Buffer (PLB) and PosMap compression techniques to reduce the performance overhead from Recursive ORAM empirically (the latter also improves the construction asymptotically). Through simulation, we show that these techniques reduce the memory bandwidth overhead needed to support recursion by 95%, reduce overall ORAM bandwidth by 37% and improve overall SPEC benchmark performance by 1.27x. We then show how our PosMap compression techniques further facilitate an extremely efficient integrity verification scheme for ORAM which we call PosMap MAC (PMMAC). For a practical parameterization, PMMAC reduces the amount of hashing needed for integrity checking by >= 68x relative to prior schemes and introduces only 7% performance overhead. We prototype our mechanisms in hardware and report area and clock frequency for a complete ORAM design post-synthesis and post-layout using an ASIC flow in a 32~nm commercial process. With 2 DRAM channels, the design post-layout runs at 1~GHz and has a total area of .47~mm2. Depending on PLB-specific parameters, the PLB accounts for 10% to 26% area. PMMAC costs 12% of total design area. Our work is the first to prototype Recursive ORAM or ORAM with any integrity scheme in hardware.
Starting Page	103
Ending Page	116
Page Count	14
File Format	PDF
ISBN	9781450328357
DOI	10.1145/2694344.2694353
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-03-14
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Oblivious ram Security Secure processor
Content Type	Text
Resource Type	Article

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