NDLI: SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance

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SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance

Content Provider	ACM Digital Library
Author	Jiang, Lei Wang, Rujia Yang, Jun Zhang, Youtao
Abstract	Phase Change Memory (PCM) has better scalability and smaller cell size comparing to DRAM. However, further scaling PCM cell in deep sub-micron regime results in significant thermal based write disturbance (WD). Naively allocating large inter-cell space increases cell size from $4F^{2}$ ideal to $12F^{2}.$ While a recent work mitigates WD along word-lines through disturbance resilient data encoding, it is ineffective for WD along bit-lines, which is more severe due to widely adopted \$\mu\$Trench structure in constructing PCM cell arrays. Without mitigating WD along bit-lines, a PCM cell still has 8F2, which is 100% larger than the ideal. In this paper, we propose SD-PCM for achieving reliable write operations in super dense PCM. In particular, we focus on mitigating WD along bit-lines such that we can construct super dense PCM chips with $4F^{2}$ cell size, i.e., the minimal for diode-switch based PCM. Based on simple verification-n-correction (VnC), we propose LazyCorrection and PreRead to effectively reduce VnC overhead and minimize cascading verification during write. We further propose (n:m)-Alloc for achieving good tradeoff between VnC overhead minimization and memory capacity loss. Our experimental results show that, comparing to a WD-free low density PCM, SD-PCM achieves 80% capacity improvement in cell arrays while incurring around 0-10% performance degradation when using different (n:m) allocators.
Starting Page	19
Ending Page	31
Page Count	13
File Format	PDF
ISBN	9781450328357
DOI	10.1145/2694344.2694352
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-03-14
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Phase change memory Write disturbance
Content Type	Text
Resource Type	Article

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SD-PCM:Constructing Reliable Super Dense Phase Change Memory under Write Disturbance (CARN, Vol. 43, Issue. 1)

SD-PCM:Constructing Reliable Super Dense Phase Change Memory under Write Disturbance (SIGP, Vol. 50, Issue. 4)

Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory

Exploit imbalanced cell writes to mitigate write disturbance in dense Phase Change Memory

Mitigating Write Disturbance in Super-Dense Phase Change Memories

Reliable, low-power super-lattice phase-change memory without melting and write-pulse down slope

PCM-Based Durable Write Cache for Fast Disk I/O

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SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance

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SD-PCM:Constructing Reliable Super Dense Phase Change Memory under Write Disturbance (CARN, Vol. 43, Issue. 1)

SD-PCM:Constructing Reliable Super Dense Phase Change Memory under Write Disturbance (SIGP, Vol. 50, Issue. 4)

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SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance