NDLI: Fast high-level power estimation for control-flow intensive design

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Fast high-level power estimation for control-flow intensive design

Content Provider	ACM Digital Library
Author	Jha, Niraj K. Lakshminarayana, Ganesh Khouri, Kamal S.
Abstract	In this paper, we present a power estimation technique for control-flow intensive designs that is tailored towards driving iterative high-level synthesis systems, where hundreds of architectural trade-offs are explored and compared. Our method is fast and relatively accurate. The algorithm utilizes the behavioral information to extract branch probabilities, and uses these in conjunction with switching activity and circuit capacitance information, to estimate the power consumption of a given architecture.We test our algorithm using a series of experiments, each geared towards measuring a different indicator. The first set of experiments measures the algorithm's accuracy when compared to the actual circuit power. The second set of experiments measures the average tracking index, and tracking index fidelity for a series of architectures. This index measures how well the algorithm makes decisions when comparing the relative power consumption of two architectures contending as low-power candidates.Results indicate that our algorithm achieved an average estimation error of 11.8% and an average tracking index of 0.95 over all examples.
Starting Page	299
Ending Page	304
Page Count	6
File Format	PDF
ISBN	1581130597
DOI	10.1145/280756.280941
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1998-08-10
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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