NDLI: A hardware/software partitioning algorithm for SIMD processor cores

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A hardware/software partitioning algorithm for SIMD processor cores

Content Provider	ACM Digital Library
Author	Togawa, Nozomu Yanagisawa, Masao Ohtsuki, Tatsuo Tachikake, Koichi Miyaoka, Yuichiro Choi, Jinku
Abstract	This paper proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions, a timing constraint of execution time, and available hardware units, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume an initial processor core on which an input assembly code can run with the shortest execution time. Secondly we reduce a hardware unit added to a processor core one by one while the timing constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally obtain a processor core architecture with small area under the given timing constraint. We expect that we can obtain a processor core which has appropriate SIMD functional units for running the input application program. The promising experimental results are also shown.
Starting Page	135
Ending Page	140
Page Count	6
File Format	PDF
ISBN	0780376609
DOI	10.1145/1119772.1119799
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-01-21
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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