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  1. Proceedings of the 2014 International Workshop on Network on Chip Architectures (NoCArc '14)
  2. Guaranteed Services of the NoC of a Manycore Processor
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Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs
Tree-Mesh Heterogeneous Topology for Low-Latency NoC
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration
Guaranteed Services of the NoC of a Manycore Processor
The Connection-Then-Credit Flow Control Protocol for Networks-On-Chips: Implementation Trade-offs
OpenSoC Fabric: On-Chip Network Generator: Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric
An Energy Efficient Load Balancing Selection Strategy for Adaptive NoC Routers
Evaluating the Feasibility of Wireless Networks-on-Chip Enabled by Graphene
A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI

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Guaranteed Services of the NoC of a Manycore Processor

Content Provider ACM Digital Library
Author de Dinechin, Benoît Dupont Durand, Yves van Amstel, Duco Ghiti, Alexandre
Abstract The Kalray MPPA®-256 processor (Multi-Purpose Processing Array) integrates 256 processing engine (PE) cores and 32 resource management (RM) cores on a single 28nm CMOS chip. These cores are distributed across 16 compute clusters and 4 I/O subsystems. On-chip communications and synchronization are supported by an explicitly routed dual data & control network-on-chip (NoC), with one node per compute cluster and 4 nodes per I/O subsystem, for a total of 32 nodes. The data NoC is dedicated to streaming data transfers and may operate with guaranteed services, thanks to non-blocking routers and flow regulation at the source node. Its architecture has been designed so that (σ, ρ) network calculus applies with minimal approximations. Given a set of flows across this data NoC with predetermined routes, we formulate the problem of guaranteeing fair allocation of bandwidth across flows and we present bounds on the maximum transfer latency. By considering the architecture of the data NoC and by introducing conservative approximations, we show how this formulation can be transformed into a linear program. Solving this linear program is efficient and the quality of its solutions appears comparable to those of the original formulation, based on problem instances obtained from the cyclostatic dataflow compilation toolchain of the Kalray MPPA®-256 processor.
Starting Page 11
Ending Page 16
Page Count 6
File Format PDF
ISBN 9781450330640
DOI 10.1145/2685342.2685344
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2014-12-13
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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