NDLI: POSTER: Exploiting Dynamic Partial Reconfiguration for Improved Resistance Against Power Analysis Attacks on FPGAs

Please wait, while we are loading the content...

The Ultimate Frontier for Privacy and Security: Medicine

Fingerprinting Wi-Fi Devices Using Software Defined Radios

Profiling the Strength of Physical-Layer Security: A Study in Orthogonal Blinding

Exploiting Data-Usage Statistics for Website Fingerprinting Attacks on Android

Don't Touch that Column: Portable, Fine-Grained Access Control for Android's Native Content Providers

Constructive and Destructive Aspects of Adaptive Wormholes for the 5G Tactile Internet

More Semantics More Robust: Improving Android Malware Classifiers

DARPA: Device Attestation Resilient to Physical Attacks

DEMO: Demonstrating Practical Known-Plaintext Attacks against Physical Layer Security in Wireless MIMO Systems

Defeating MAC Address Randomization Through Timing Attacks

Interleaving Jamming in Wi-Fi Networks

Can Android Applications Be Identified Using Only TCP/IP Headers of Their Launch Time Traffic?

Shatter: Using Threshold Cryptography to Protect Single Users with Multiple Devices

A Prover-Anonymous and Terrorist-Fraud Resistant Distance-Bounding Protocol

Evading Android Runtime Analysis Through Detecting Programmed Interactions

Dissecting Customized Protocols: Automatic Analysis for Customized Protocols based on IEEE 802.15.4

DEMO: Far Away and Yet Nearby - A Framework for Practical Distance Fraud on Proximity Services for Mobile Devices

Trust The Wire, They Always Told Me!: On Practical Non-Destructive Wire-Tap Attacks Against Ethernet

Slogger: Smashing Motion-based Touchstroke Logging with Transparent System Noise

Vibreaker: Securing Vibrational Pairing with Deliberate Acoustic Noise

Secure Motion Verification using the Doppler Effect

Detecting SMS Spam in the Age of Legitimate Bulk Messaging

Smart-Phones Attacking Smart-Homes

DEMO: Panoptiphone: How Unique is Your Wi-Fi Device?

DEMO: Using NexMon, the C-based WiFi firmware modification framework

POSTER: Assessing the Impact of 802.11 Vulnerabilities using Wicability

POSTER: Design Ideas for Privacy-aware User Interfaces for Mobile Devices

POSTER: Experimental Analysis of Popular Anonymous, Ephemeral, and End-to-End Encrypted Apps

POSTER: Exploiting Dynamic Partial Reconfiguration for Improved Resistance Against Power Analysis Attacks on FPGAs

POSTER: Friend or Foe? Context Authentication for Trust Domain Separation in IoT Environments

POSTER: Security Design Patterns With Good Usability

POSTER: Toward a Secure and Scalable Attestation

POSTER: Exploiting Dynamic Partial Reconfiguration for Improved Resistance Against Power Analysis Attacks on FPGAs

Content Provider	ACM Digital Library
Author	Dessouky, Ghada Sadeghi, Ahmad-Reza
Abstract	FPGA devices are increasingly deployed in wireless and heterogeneous networks in-field due to their re-programmable nature and high performance. Modern FPGA devices can have part of their logic partially reconfigured during runtime operation, which we propose to exploit to realize a general-purpose, flexible and reconfigurable DPA countermeasure that can be integrated into any FPGA-based system, irrespective of the cryptographic algorithm or implementation. We propose a real-time dynamic closed-loop on-chip noise generation countermeasure which consists of an on-chip power monitor coupled with a low-overhead Gaussian noise generator. The noise generator is reconfigured continuously to update its generated noise amplitude and variance so that is sufficiently hides the computation power consumption. Our scheme and its integration onto an SoC is presented as well as our proposal for evaluating its effectiveness and overhead.
Starting Page	223
Ending Page	224
Page Count	2
File Format	PDF
ISBN	9781450342704
DOI	10.1145/2939918.2942426
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2016-07-18
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpga Partial dynamic logic reconfiguration Power analysis attacks Noise generator
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting

Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration

Dynamic Partial Reconfiguration in FPGAs for DSP Applications

Dynamic Partial Reconfiguration in FPGAs

Avoiding transitional effects in dynamic circuit specialisation on FPGAs

On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives

Run-Time FPGA Reconfiguration for Power-/CostOptimized Real-Time Systems

On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs

Dynamic specialisation of xc6200 fpgas by partial evaluation. Fieldprogrammable logic and applications (1998).

POSTER: Exploiting Dynamic Partial Reconfiguration for Improved Resistance Against Power Analysis Attacks on FPGAs

Similar Documents

FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting

Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration

Dynamic Partial Reconfiguration in FPGAs for DSP Applications

Dynamic Partial Reconfiguration in FPGAs

Avoiding transitional effects in dynamic circuit specialisation on FPGAs

On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives

Run-Time FPGA Reconfiguration for Power-/CostOptimized Real-Time Systems

On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs

Dynamic specialisation of xc6200 fpgas by partial evaluation. Fieldprogrammable logic and applications (1998).

POSTER: Exploiting Dynamic Partial Reconfiguration for Improved Resistance Against Power Analysis Attacks on FPGAs