NDLI: Distributed cooperative caching

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Outer-loop vectorization: revisited for short SIMD architectures

Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults

The PARSEC benchmark suite: characterization and architectural implications

MCAMP: communication optimization on massively parallel machines with hierarchical scratch-pad memory

Distributed cooperative caching

Edge-centric modulo scheduling for coarse-grained reconfigurable architectures

Leveraging on-chip networks for data cache migration in chip multiprocessors

An adaptive resource partitioning algorithm for SMT processors

Prediction models for multi-dimensional power-performance optimization on many cores

A tuning framework for software-managed memory hierarchies

GPU evolution: will graphics morph into compute?

Redundancy elimination revisited

Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor

Visualizing potential parallelism in sequential programs

Profiler and compiler assisted adaptive I/O prefetching for shared storage caches

Scalable and reliable communication for hardware transactional memory

Multi-optimization power management for chip multiprocessors

Adaptive insertion policies for managing shared caches

Meeting points: using thread criticality to adapt multicore hardware to parallel regions

Mars: a MapReduce framework on graphics processors

Hybrid access-specific software cache techniques for the cell BE architecture

(How) can programmers conquer the multicore menace?

Exploiting loop-dependent stream reuse for stream processors

Skewed redundancy

Characterizing and modeling the behavior of context switch misses

Runtime optimization of vector operations on large scale SMP clusters

Improving support for locality and fine-grain sharing in chip multiprocessors

Multitasking workload scheduling on flexible-core chip multiprocessors

Analysis and approximation of optimal co-scheduling on chip multiprocessors

Multi-mode energy management for multi-tier server clusters

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Feature selection and policy optimization for distributed instruction placement using reinforcement learning

Distributed cooperative caching

Content Provider	ACM Digital Library
Author	Canal, Ramon González, José Herrero, Enric
Abstract	This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration is based in the Cooperative Caching framework [3] but it is intended for large scale CMPs. Both centralized and distributed configurations have the advantage of combining the benefits of private and shared caches. In our proposal, the Coherence Engine has been redesigned to allow its partitioning and thus, eliminate the size constraints imposed by the duplication of all tags. At the same time, a global replacement mechanism has been added to improve the usage of cache space. Our framework uses several Distributed Coherence Engines spread across all the nodes to improve scalability. The distribution permits a better balance of the network traffic over the entire chip avoiding bottlenecks and increasing performance for a 32-core CMP by 21% over a traditional shared memory configuration and by 57% over the Cooperative Caching scheme. Furthermore, we have reduced the power consumption of the entire system by using a different tag allocation method and by reducing the number of tags compared on each request. For a 32-core CMP the Distributed Cooperative Caching framework provides an average improvement of the power/performance relation $(MIPS^{3}/W)$ of 3.66x over a traditional shared memory configuration and 4.30x over Cooperative Caching.
Starting Page	134
Ending Page	143
Page Count	10
File Format	PDF
ISBN	9781605582825
DOI	10.1145/1454115.1454136
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-10-25
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Memory hierarchy Chip multiprocessors Energy efficiency
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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