NDLI: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms

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Pattern Selection for Testing of Deep Sub-Micron Timing Defects

Analyzing On-Chip Communication in a MPSoC Environment

A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs

Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach

A Case Study in Networks-on-Chip Design for Embedded Video

Exploiting Crosstalk to Speed up On-Chip Buses

False-Noise Analysis for Domino Circuits

Crosstalk Minimization in Logic Synthesis for PLA

Synthesis for Manufacturability: A Sanity Check

Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit

Impact of Test Point Insertion on Silicon Area and Timing during Layout

Designing Self Test Programs for Embedded DSP Cores

Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction

Thermal and Power Integrity Based Power/Ground Networks Optimization

Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs

DATE Panel: Chips of the Future: Soft, Crunchy or Hard?

Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks

Power-Aware Network Swapping for Wireless Palmtop PCs

Power Aware Interface Synthesis for Bus-Based SoC Designs

Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones

An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip

Bandwidth-Constrained Mapping of Cores onto NoC Architectures

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies

Fast Comparisons of Circuit Implementations

Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs

MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis

Nanometer Design: What are the Requirements for Manufacturing Test?

Poor Man's TBR: A Simple Model Reduction Scheme

Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals

SCORE: SPICE COmpatible Reluctance Extraction

A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk

A Framework for Battery-Aware Sensor Management

Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance

An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology

Smaller Two-Qubit Circuits for Quantum Communication and Computation

Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing

Measurement of IP Qualification Costs and Benefits

Architecture-Level Performance Estimation for IP-Based Embedded Systems

Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures

Platform Based on Open-Source Cores for Industrial Applications

MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor

Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications

Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches

Workload Characterization Model for Tasks with Variable Execution Demand

Context-Aware Performance Analysis for Efficient Embedded System Design

Compact Binaries with Code Compression in a Software Dynamic Translator

Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects

Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis

A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits

Soft Faults and the Importance of Stresses in Memory Testing

Wire Retiming for System-on-Chip by Fixpoint Computation

Boosting: Min-Cut Placement with Improved Signal Delay

Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus

A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk

Full-Chip Multilevel Routing for Power and Signal Integrity

Energy-Aware System Design for Wireless Multimedia

Unified Component Integration Flow for Multi-Processor SoC Design and Validation

An Interconnect Channel Design Methodology for High Performance Integrated Circuits

Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach

Supporting Cache Coherence in Heterogeneous Multiprocessor Systems

Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors

Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications

Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems

Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks

Status of IEEE Testability Standards 1149.4, 1532 and 1149.6

Eliminating False Positives in Crosstalk Noise Analysis

A New Approach to Timing Analysis Using Event Propagation and Temporal Logic

A New Effective Congestion Model in Floorplan Design

ULSI Interconnect Length Distribution Model Considering Core Utilization

Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study

Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays

Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience

Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing

A Power and Performance Model for Network-on-Chip Architectures

A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms

Cache-Aware Scratchpad Allocation Algorithm

Phase Coupled Code Generation for DSPs Using a Genetic Algorithm

A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models

Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression

CircularScan: A Scan Architecture for Test Cost Reduction

Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets

Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes

Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation

Direct Nonlinear Order Reduction with Variational Analysis

Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method

Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits

System Verilog for VHDL Users

Distributed Multimedia System Design: A Holistic Perspective

Adaptive Prefetching for Multimedia Applications in Embedded Systems

Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases

High-Performance QuIDD-Based Simulation of Quantum Circuits

An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation

Fault Tolerance of Programmable Switch Blocks

A New Self-Checking Sum-Bit Duplicated Carry-Select Adder

A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation

Accurate Estimation of Parasitic Capacitances in Analog Circuits

GRAAL -- A Development Framework for Embedded Graphics Accelerators

From Synchronous to Asynchronous: An Automatic Approach

Enhancing Testability of System on Chips Using Network Management Protocols

Minimization of Crosstalk Noise, Delay and Power Using a Modi.ed Bus Invert Technique

Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors

Dynamic Voltage and Cache Reconfiguration for Low Power

Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models

Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software

Synthesis of Reversible Logic

A Unified Design Space for Regular Parallel Prefix Adders

MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions

Issues in Implementing Latency Insensitive Protocols

Model-Based Specification and Execution of Embedded Real-Time Systems

A Demonstration of Co-Design and Co-Verification in a Synchronous Language

Profile Guided Management of Code Partitions for Embedded Systems

Realizable Reduction for Electromagnetically Coupled RLMC Interconnects

Statistically Aware Buffer Planning

A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology

Power Supply Noise Monitor for Signal Integrity Faults

Testing of Quantum Dot Cellular Automata Based Designs

Net and Pin Distribution for 3D Package Global Routing

Placement Using a Localization Probability Model (LPM)

CMOS Structures Suitable for Secured Hardware

Timing Correction and Optimization with Adaptive Delay Sequential Elements

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