NDLI: System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip

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Static scheduling of multi-domain memories for functional verification

System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip

Analysis of substrate thermal gradient effects on optimal buffer insertion

Behavioral modeling of analog circuits by wavelet collocation method

Sequential SPFDs

CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors

Interconnect resource-aware placement for hierarchical FPGAs

Area minimization of power distribution network using efficient nonlinear programming techniques

Min-area retiming on flexible circuit structures

An assembly-level execution-time model for pipelined architectures

Congestion aware layout driven logic synthesis

Techniques for including dielectrics when extracting passive low-order models of high speed interconnect

Low power system scheduling and synthesis

CAD solutions and outstanding challenges for mixed-signal and RFIC design

Efficient conflict driven learning in a boolean satisfiability solver

Symbolic algebra and timing driven data-flow synthesis

Formulae and applications of interconnect estimation considering shield insertion and net ordering

The sizing rules method for analog integrated circuit design

On identifying don't care inputs of test patterns for combinational circuits

Color permutation: an iterative algorithm for memory packing

Multilevel approach to full-chip gridless routing

Highly accurate fast methods for extraction and sparsification of substrate coupling based on low-rank approximation

BOOM: a heuristic boolean minimizer

Energy efficient real-time scheduling

Multigrid-like technique for power grid analysis

A symbolic simulation-based methodology for generating black-box timing models of custom macrocells

The design and optimization of SOC test solutions

Transient power management through high level synthesis

Local search for final placement in VLSI design

Model reduction of variable-geometry interconnects using variational spectrally-weighted balanced truncation

Single-pass redundancy addition and removal

A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA

IC power distribution challenges

Automatic hierarchical design: fantasy or reality?

A simulation-based method for the verification of shared memory in multiprocessor systems

System level design with spade: an M-JPEG case study

A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

Simulation-based automatic generation of signomial and posynomial performance models for analog integrated circuit sizing

On the optimization power of redundancy addition and removal techniques for sequential circuits

Software-assisted cache replacement mechanisms for embedded systems

A router for symmetrical FPGAs based on exact routing density evaluation

Coupled analysis of electromigration reliability and performance in ULSI signal nets

Verification of integer multipliers on the arithmetic bit level

Improving memory energy using access pattern classification

Addressing the timing closure problem by integrating logic optimization and placement

A convex programming approach to positive real rational approximation

Internal design representations for embedded systems: extended abstract of embedded tutorial

Partition-based decision heuristics for image computation using SAT and BDDs

Application-driven processor design exploration for power-performance trade-off analysis

Hybrid structured clock network construction

ASF: a practical simulation-based methodology for the synthesis of custom analog circuits

REDI: an efficient fault oriented procedure to identify redundant faults in combinational logic circuits

Constraint satisfaction for relative location assignment and scheduling

A force-directed maze router

Fast 3-D inductance extraction in lossy multi-layer substrate

Faster SAT and smaller BDDs via common function structure

Efficient performance estimation for general real-time task systems

An analytical high-level battery model for use in energy management of portable electronic systems

On the signal bounding problem in timing analysis

Accurate CMOS bridge fault modeling with neural network-based VHDL saboteurs

An integrated data path optimization for low power based on network flow method

Congestion reduction during placement based on integer programming

Improving the robustness of a surface integral formulation for wideband impendance extraction of 3D structures

Efficient canonical form for boolean matching of complex functions in large libraries

Area and power reduction of embedded DSP systems using instruction compression and re-configurable encoding

Challenges in power-ground integrity

Predicting the performance of synchronous discrete event simulation systems

NetBench: a benchmarking suite for network processors

Bus encoding to prevent crosstalk delay

Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method

Placement driven retiming with a coupled edge timing model

Instruction generation for hybrid reconfigurable systems

A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs

Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects

Induction-based gate-level verification of multipliers

System-level power/performance analysis of portable multimedia systems communicating over wireless channels

An algorithm for simultaneous pin assignment and routing

A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices

Optimisation problems for dynamic concurrent task-based systems

Non-linear quantification scheduling in image computation

A system for synthesizing optimized FPGA hardware from MATLAB

CASh: a novel "clock as shield" design methodology for noise immune precharge-evaluate logic

A layout-aware synthesis methodology for RF circuits

Crosstalk fault detection by dynamic Idd

A super-scheduler for embedded reconfigurable systems

Minimum-buffered routing of non-critical nets for slew rate and reliability control

Simulation approaches for strongly coupled interconnect systems

Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits

STARS in VCC: complementing simulation with worst-case analysis

Power-delay modeling of dynamic CMOS gates for circuit optimization

False-noise analysis using logic implications

Algorithm level re-computing: a register transfer level concurrent error detection technique

What is the limit of energy saving by dynamic voltage scaling?

Direct transistor-level layout for digital blocks

Practical considerations in RLCK crosstalk analysis for digital integrated circuits

Compatible observability don't cares revisited

I-CoPES: fast instruction code placement for embedded systems to improve performance and energy efficiency

Solution of parallel language equations for logic synthesis

Panel: will nanotechnology change the way we design and verify systems?

Behavior-to-placed RTL synthesis with performance-driven placement

A probabilistic constructive approach to optimization problems

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