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| Content Provider | ACM Digital Library |
|---|---|
| Author | So, Won Dean, Alexander G. |
| Abstract | Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in high-performance embedded applications such as digital signal processing. Software thread integration (STI) can often improve the performance of looping code in cases where software pipelining performs poorly or fails. This paper examines both situations, presenting methods to determine what and when to integrate.We evaluate our methods on C-language image and digital signal processing libraries and synthetic loop kernels. We compile them for a very long instruction word (VLIW) digital signal processor (DSP) -- the Texas Instruments (TI) C64x architecture. Loops which benefit little from software pipelining (SWP-Poor) speed up by 26% (harmonic mean, HM). Loops for which software pipelining fails (SWP-Fail) due to conditionals and calls speed up by 16% (HM). Combining SWP-Good and SWP-Poor loops leads to a speedup of 55% (HM). |
| Starting Page | 137 |
| Ending Page | 146 |
| Page Count | 10 |
| File Format | |
| ISBN | 1595930183 |
| DOI | 10.1145/1065910.1065930 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2005-06-15 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Dsp Stream programming Coarse-grain parallelism Software thread integration Ti c6000 Vliw Software pipelining |
| Content Type | Text |
| Resource Type | Article |
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