NDLI: Minimization of supervisor conflict for multiprocessor computer systems

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Volume 28

Volume 27

Volume 7, Issue 4, July 1976

A study of interleaved memory systems by trace driven simulation

A dynamic clustering strategy in a demand paging environment

I/O buffer performance in a virtual memory system

Statistical analysis of simulation output data

A simulation method for multi-level data security analysis

Minimization of supervisor conflict for multiprocessor computer systems

A heuristic teleprocessing network design technique

Trace Driven modeling

Workload classification

Relationship of software engineering and simulation

Experience with the central server model on a lightly-loaded system

Experience with trace driven modeling

Run-time characteristics of a simulation model

When to stop a simulation run

An introduction to the simulation of a multiple CPU military communications system

Management of a large computer network simulation project

A queuing model with discrete service speeds

Program testing techniques using simulated execution

A Diagnostic Emulator for HEAO software development

Testing of microprograms using the lockheed SUE microinstruction simulator

Workshop session

Production and representation of computer system simulation models

Processor System Modeling - a language and simulation system

Volume 7, Issue 3, April 1976

Volume 7, Issue 2, January 1976

Volume 7, Issue 1, October 1975

Minimization of supervisor conflict for multiprocessor computer systems

Content Provider	ACM Digital Library
Author	Raynor, Randy J. Gwynn, John M.
Abstract	In a multiprocessor system, the handling of interrupts generated by jobs in the processors is assigned to a supervisory program and associated data base. The two basic philosophies for deciding which processor executes the supervisor are master-slave and floating executive control. In either case, queueing of requests to the supervisor may occur. With the master-slave structure, the master processor can handle only one request at a time. With floating executive control, while any processor can execute the supervisor, only one processor at a time can be allowed to access the supervisor's data base. A processor which is waiting to use the supervisor is not doing useful work. Therefore, queueing of requests to the supervisor causes a degradation in the performance of the system. Previous studies have indicated that this degradation is significant for systems with a large number of processors. A methodology is developed through simulation which reduces supervisor queueing by scheduling jobs to processors such that they request the use of the supervisor when the supervisor is predicted to be available. Information concerning job execution characteristics required by the scheduler is shown to be available at sufficient accuracy via dynamic monitoring and forecasting during normal program execution.
Starting Page	61
Ending Page	69
Page Count	9
File Format	PDF
ISSN	01636103
DOI	10.1145/1013610.807300
Journal	ACM SIGSIM Simulation Digest (SIML)
Volume Number	7
Issue Number	4
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1990-12-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Minimization of supervisor conflict for multiprocessor computer systems

Performance analysis of redundant-path networks for multiprocessor systems

On the Memory Conflict Problem in Multiprocessor Systems

Markov chain models for analyzing memory interference in multiprocessor computer systems

Performance evaluation of RUNT algorithm

A survey of hard real-time scheduling for multiprocessor systems

Transaction Scheduling Using Dynamic Conflict Avoidance

Experience Using Multiprocessor Systems—A Status Report

Banyan networks for partitioning multiprocessor systems

Minimization of supervisor conflict for multiprocessor computer systems

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