NDLI: Ultra low-cost defect protection for microprocessor pipelines (OPSR, Vol. 40, Issue. 5)

Content Provider	ACM Digital Library
Author	Shyam, Smitha Constantinides, Kypros Bertacco, Valeria Austin, Todd Phadke, Sujay
Abstract	The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost. Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode. Using detailed circuit-level and architectural simulation, we find that our approach provides very high coverage of silicon defects (89%) with little area cost (5.8%). In addition, when a defect occurs, the subsequent degraded mode of operation was found to have only moderate performance impacts, (from 4% to 18% slowdown).
Starting Page	73
Ending Page	82
Page Count	10
File Format	PDF
ISSN	01635980
DOI	10.1145/1168917.1168868
Journal	ACM SIGOPS Operating Systems Review (OPSR)
Volume Number	40
Issue Number	5
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1975-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Low-cost Pipelines Defect-protection Reliability
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture Information Systems

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Ultra low-cost defect protection for microprocessor pipelines (CARN, Vol. 34, Issue. 5)

Ultra low-cost defect protection for microprocessor pipelines (SIGP, Vol. 41, Issue. 11)

Mondrian memory protection (OPSR, Vol. 36, Issue. 5)

Impact of virtualization on computer architecture and operating systems (OPSR, Vol. 40, Issue. 5)

Stealth prefetching (OPSR, Vol. 40, Issue. 5)

Hybrid transactional memory (OPSR, Vol. 40, Issue. 5)

Tartan:evaluating spatial computation for whole program execution (OPSR, Vol. 40, Issue. 5)

A defect tolerant self-organizing nanoscale SIMD architecture (OPSR, Vol. 40, Issue. 5)

Combinatorial sketching for finite programs (OPSR, Vol. 40, Issue. 5)

Ultra low-cost defect protection for microprocessor pipelines (OPSR, Vol. 40, Issue. 5)

Similar Documents

Ultra low-cost defect protection for microprocessor pipelines (CARN, Vol. 34, Issue. 5)

Ultra low-cost defect protection for microprocessor pipelines (SIGP, Vol. 41, Issue. 11)

Mondrian memory protection (OPSR, Vol. 36, Issue. 5)

Impact of virtualization on computer architecture and operating systems (OPSR, Vol. 40, Issue. 5)

Stealth prefetching (OPSR, Vol. 40, Issue. 5)

Hybrid transactional memory (OPSR, Vol. 40, Issue. 5)

Tartan:evaluating spatial computation for whole program execution (OPSR, Vol. 40, Issue. 5)

A defect tolerant self-organizing nanoscale SIMD architecture (OPSR, Vol. 40, Issue. 5)

Combinatorial sketching for finite programs (OPSR, Vol. 40, Issue. 5)

Ultra low-cost defect protection for microprocessor pipelines (OPSR, Vol. 40, Issue. 5)