NDLI: Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory

Content Provider	ACM Digital Library
Author	Hao, Jeff Hsu, Po-Chun Mahlke, Scott Mehrara, Mojtaba
Abstract	Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performance for most applications. The industry has already fallen short of the decades-old performance trend of doubling performance every 18 months. An attractive approach for exploiting multiple cores is to rely on tools, both compilers and runtime optimizers, to automatically extract threads from sequential applications. However, despite decades of research on automatic parallelization, most techniques are only effective in the scientific and data parallel domains where array dominated codes can be precisely analyzed by the compiler. Thread-level speculation offers the opportunity to expand parallelization to general-purpose programs, but at the cost of expensive hardware support. In this paper, we focus on providing low-overhead software support for exploiting speculative parallelism. We propose STMlite, a light-weight software transactional memory model that is customized to facilitate profile-guided automatic loop parallelization. STMlite eliminates a considerable amount of checking and locking overhead in conventional software transactional memory models by decoupling the commit phase from main transaction execution. Further, strong atomicity requirements for generic transactional memories are unnecessary within a stylized automatic parallelization framework. STMlite enables sequential applications to extract meaningful performance gains on commodity multicore hardware.
Starting Page	166
Ending Page	176
Page Count	11
File Format	PDF
ISSN	03621340 15581160
DOI	10.1145/1543135.1542495
Journal	ACM SIGPLAN Notices (SIGP)
Volume Number	44
Issue Number	6
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1983-05-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Automatic parallelization Software transactional memory Profile-guided optimization Thread-level speculation Loop level parallelism
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software

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Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory

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