NDLI: Improving cache performance with balanced tag and data paths (SIGP, Vol. 31, Issue. 9)

Content Provider	ACM Digital Library
Author	Ong, Shauchi Peir, Jih-Kwon Young, Honesty Hsu, Windsor W.
Abstract	There are two concurrent paths in a typical cache access --- one through the data array and the other through the tag array. The path through the data array drives the selected set out of the array. The path through the tag array determines cache hit/miss and, for set-associative caches, selects the appropriate line from within the selected set. In both direct-mapped and set-associative caches, the path through the tag array is significantly longer than that through the data array. In this paper, we propose a path balancing technique help match the delays of the tag and data paths. The basic idea behind this technique is to employ a separate subset of the tag array to decouple the one-to-one relationship between address tags and cache lines so as to achieve a design that provides higher performance. Performance evaluation using both TPC-C and SPEC92 benchmarks shows that this path balancing technique offers impressive improvements in overall system performance over conventional cache designs. For TPC-C, improvements in the range of 6% to 28% are possible.
Starting Page	268
Ending Page	278
Page Count	11
File Format	PDF
ISSN	03621340 15581160
DOI	10.1145/248209.237202
Journal	ACM SIGPLAN Notices (SIGP)
Volume Number	31
Issue Number	9
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1983-05-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software

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