NDLI: Enabling compiler flow for embedded VLIW DSP processors with distributed register files

Content Provider	ACM Digital Library
Author	Lu, Chia-Han Tseng, Ling-Hua Chen, Chung-Kai Chen, Shih-Chang You, Yi-Ping Lin, Young-Jia Lee, Jenq-Kuen
Abstract	High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in designs of VLIW DSP processors, distributed register files and multi-bank register architectures are being adopted to eliminate the amount of read/write ports in register files. This presents new challenges for devising compiler optimization schemes for such architectures. In this paper, we address the compiler optimization issues for PAC architecture, which is a 5-way issue DSP processor with distributed register files. We present an integrated flow to address several phases of compiler optimizations in interacting with distributed register files and multi-bank register files in the layer of instruction scheduling, software pipelining, and data flow optimizations. Our experiments on a novel 32-bit embedded VLIW DSP (known as the PAC DSP core) exhibit the state of the art performance for embedded VLIW DSP processors with distributed register files by incorporating our proposed schemes in compilers.
Starting Page	146
Ending Page	148
Page Count	3
File Format	PDF
ISSN	03621340 15581160
DOI	10.1145/1273444.1254793
Journal	ACM SIGPLAN Notices (SIGP)
Volume Number	42
Issue Number	7
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1983-05-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Embedded vliw dsp compilers Distributed register files Software pipelining
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software

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Enabling compiler flow for embedded VLIW DSP processors with distributed register files

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