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| Content Provider | ACM Digital Library |
|---|---|
| Author | Torrellas, Josep Qian, Xuehai Qian, Depei Sahelices, Benjamin |
| Abstract | Sequential Consistency (SC) is the most intuitive memory model, and SC Violations (SCVs) produce unintuitive, typically incorrect executions. Most prior SCV detection schemes have used data races as proxies for SCVs, which is highly imprecise. Other schemes that have targeted data-race cycles are either too conservative or are designed only for two-processor cycles and snoopy-based systems. This paper presents Volition, the first hardware scheme that detects SCVs in a relaxed-consistency machine precisely, in a scalable manner, and for an arbitrary number of processors in the cycle. Volition leverages cache coherence protocol transactions to dynamically detect cycles in memory-access orders across threads. When a cycle is about to occur, an exception is triggered. Volition can be used in both directory- and snoopy-based coherence protocols. Our simulations of Volition in a 64-processor multicore with directory-based coherence running SPLASH-2 and Parsec programs shows that Volition induces negligible traffic and execution overhead. In addition, it can detect SCVs with several processors. Volition is suitable for on-the-fly use. |
| Starting Page | 535 |
| Ending Page | 548 |
| Page Count | 14 |
| File Format | |
| ISSN | 03621340 15581160 |
| DOI | 10.1145/2499368.2451174 |
| Journal | ACM SIGPLAN Notices (SIGP) |
| Volume Number | 48 |
| Issue Number | 4 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1983-05-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Parallel programming Shared-memory multiprocessors Sequential consistency Memory consistency |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Software |
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