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| Content Provider | ACM Digital Library |
|---|---|
| Author | Cullmann, Christoph |
| Abstract | To compute a worst-case execution time (WCET) estimate for a program, the architectural effects of the underlying hardware must be modeled. For modern processors this results in the need for a cache and pipeline analysis. The timing-relevant result of the cache analysis is the categorization of the accesses to cached memory. Categorizations that are obtainable by the well-known must and may cache analysis are always-hit, always-miss and not-classified. The cache persistence analysis tries to provide additional information for the not-classified case to limit the number of misses. There exists a cache persistence analysis by Ferdinand and Wilhelm based on abstract interpretation computing these classifications. In this paper, we present a correctness issue with this analysis and a novel analysis that fixes it. For fully timing compositional architectures the persistence information is straightforward to use. We will focus on the application of the persistence analysis for state-of-the-art architectures that show timing anomalies. Such architectures do not allow to quantify the costs of a single cache hit or miss in isolation. To make the usage of the persistence information feasible, we integrate the novel persistence analysis together with a novel path analysis approach into the industrially used WCET analyzer aiT. |
| Starting Page | 121 |
| Ending Page | 130 |
| Page Count | 10 |
| File Format | |
| ISSN | 03621340 15581160 |
| DOI | 10.1145/2016603.1967695 |
| Journal | ACM SIGPLAN Notices (SIGP) |
| Volume Number | 46 |
| Issue Number | 5 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1983-05-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Persistence Wcet Cache |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Software |
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