NDLI: Static bus schedule aware scratchpad allocation in multiprocessors

Content Provider	ACM Digital Library
Author	Roychoudhury, Abhik Chattopadhyay, Sudipta
Abstract	Compiler controlled memories or scratchpad memories offer more predictable program execution times than cache memories. Scratchpad memories are often employed in multi-processor system-on-chip (MPSoC) platforms which seek to meet the performance needs of embedded applications while limiting power consumption and timing unpredictability. Scratchpad allocation schemes optimize performance while ensuring predictable execution times (as compared to caches). In this work, we develop a compile-time scratchpad allocation framework for multi-processor platforms, where the processors (virtually) share on-chip scratchpad space and external memory is accessed through a shared bus. Our allocation method considers the waiting time for bus access while deciding which memory blocks to load into the shared scratchpad memory space. Incorporating the bus schedule into our scratchpad allocation method leads to a global optimization of an application, as compared to employing local scratchpad allocation schemes in individual processors which locally optimize the per-processor execution time. We evaluate the efficacy, sensitivity and efficiency of our memory allocation scheme on two real-world embedded applications - an application controlling an Unmanned Aerial Vehicle (UAV), and a (fragment of) an in-orbit spacecraft software.
Starting Page	11
Ending Page	20
Page Count	10
File Format	PDF
ISSN	03621340 15581160
DOI	10.1145/2016603.1967680
Journal	ACM SIGPLAN Notices (SIGP)
Volume Number	46
Issue Number	5
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1983-05-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Wcet Mpsoc Scratchpad Shared bus
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software

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